公开(公告)号：GB2492444A

公开(公告)日：2013-01-02

申请号：GB201208147

申请日：2012-05-10

Applicant: IBM

Inventor： BEDELL STEPHEN ,  FOGEL KEITH ,  LAURO PAUL ,  CORTES NORMA EDITH SOSA ,  SHAHRJERDI DAVOOD ,  SADANA DEVENDRA

IPC: H01L31/18

Abstract: A method to minimize edge-related substrate breakage during spalling using an edge-exclusion region (14) where the stressor layer (16) is either non-present (excluded either during deposition or removed afterwards) or present but significantly non-adhered to the substrate surface in the exclusion region is provided. In a preferred embodiment of the present invention, the method includes forming an edge exclusion material (14) on an upper surface and near an edge of a base substrate (10â â ). A stressor layer (16) is then formed on exposed portions of the upper surface of the base substrate (10â â ) and atop the edge exclusion material (14). A portion (10â ) of the base substrate that is located beneath the stressor layer and which is not covered by the edge exclusion material is then spalled and separated from the bulk of the substrate. The material is removed from the substrate by stresses caused by the stressor layer. An adhesive layer (15) can be formed between the substrate and stressor layer. This method improves the reusability of the substrate.

公开(公告)号：GB2491930A

公开(公告)日：2012-12-19

申请号：GB201206430

申请日：2012-04-12

Applicant: IBM

Inventor： CHENG CHENG-WEI ,  BEDELL STEPHEN ,  SHIU KUEN-TING ,  SADANA DEVENDRA ,  CORTES NORMA EDITH SOSA

IPC: H01L21/762 ,  H01L31/18

Abstract: A method of removing a semiconductor device layer from a base substrate comprising providing a crack propagation layer 12 on an upper surface of a base substrate 10; a semiconductor device layer 14 including at least one semiconductor device is formed on the crack propagation layer 12; etching the end portions of the crack propagation layer 12 to initiate a crack in the crack propagation layer 12; the etched crack propagation layer 15 is then cleaved to provide a cleaved crack propagation layer portion to a surface of the semiconductor device layer 14 and another cleaved crack propagation layer portion to the upper surface of the base substrate 10; the cleaved crack propagation layer portion is removed from the surface of the semiconductor device layer 14 and the another cleaved crack propagation layer portion is removed from the upper surface of the base substrate 10. Prior to etching the crack propagation layer 12, a stressor 16 may be applied to the device layer; the stressor 16 may further be bonded to a polymer support 18. The present method allows for cleaving of a semiconductor device layer 14 from a substrate 10 at a controlled location.

公开(公告)号：GB2489830A

公开(公告)日：2012-10-10

申请号：GB201206801

申请日：2011-02-01

Applicant: IBM

Inventor： BEDELL STEPHEN ,  KIM JEE HWAN ,  INNS DANIEL ,  SADANA DEVENDRA ,  FOGEL KEITH ,  VICHICONTI JAMES

IPC: H01L21/18 ,  H01L21/02 ,  H01L21/30

Abstract: A method for layer transfer using a boron-doped silicon germanium (SiGe) layer includes forming a boron-doped SiGe layer on a bulk silicon substrate; forming an upper silicon (Si) layer over the boron-doped SiGe layer; hydrogenating the boron-doped SiGe layer; bonding the upper Si layer to an alternate substrate; and propagating a fracture at an interface between the boron-doped SiGe layer and the bulk silicon substrate. A system for layer transfer using a boron-doped silicon germanium (SiGe) layer includes a bulk silicon substrate; a boron-doped Si Ge layer formed on the bulk silicon substrate, such that the boron-doped SiGe layer is located underneath an upper silicon (Si) layer, wherein the boron- doped SiGe layer is configured to propagate a fracture at an interface between the boron- doped SiGe layer and the bulk silicon substrate after hydrogenation of the boron-doped SiGe layer; and an alternate substrate bonded to the upper Si layer.

公开(公告)号：AU2020384653A1

公开(公告)日：2022-04-21

申请号：AU2020384653

申请日：2020-11-10

Applicant: IBM

Inventor： HOLMES STEVEN ,  BEDELL STEPHEN ,  HART SEAN ,  SADANA DEVENDRA ,  LI NING ,  GUMANN PATRYK

IPC: H01L27/18 ,  B82Y10/00 ,  G06N10/00 ,  H01L39/22 ,  H01L39/24

Abstract: A quantum computing device is fabricated by forming, on a superconductor layer (410), a first resist pattern defining a device region and a sensing region within the device region. The superconductor layer within the sensing region is removed, exposing a region of a first surface of an underlying semiconductor layer (340) outside the device region. The exposed region of the semiconductor layer is implanted, forming an isolation region surrounding the device region. The sensing region and a portion of the device of the superconductor layer are exposed. A sensing region contact (202) is formed by coupling the first surface of the semiconductor layer with a first metal layer. A nanorod contact (206, 212) using the first metal within the portion of the device region outside the sensing region is formed. By depositing a second metal layer on a second surface of the semiconductor layer within the sensing region, a tunnel junction gate (204) is formed.

公开(公告)号：DE112019002427T5

公开(公告)日：2021-02-11

申请号：DE112019002427

申请日：2019-06-18

Applicant: IBM

Inventor： DE SOUZA JOEL PEREIRA ,  COLLINS JOHN ,  SADANA DEVENDRA ,  BEDELL STEPHEN ,  OTT JOHN ,  HOPSTAKEN MARINUS JOHANNES PETRUS

IPC: H01M10/052 ,  H01M4/134 ,  H01M4/1395 ,  H01M10/056

Abstract: Es werden wiederaufladbare Lithium-Ionen-Batterien bereitgestellt, welche eine hohe Kapazität aufweisen. Die Lithium-Ionen-Batterien enthalten eine Anodenstruktur, die von einheitlicher Konstruktion ist und eine nicht-poröse Zone und eine poröse Zone aufweist, welche eine obere poröse Schicht (Poröse Zone 1) mit einer ersten Dicke und einer ersten Porosität und eine untere poröse Schicht (Poröse Zone 2) umfasst, die unterhalb der oberen porösen Schicht angeordnet ist und eine Grenzfläche mit der nicht-porösen Zone bildet. Zumindest ein oberer Abschnitt der nicht-porösen Zone und die Gesamtheit der porösen Zone sind aus Silicium aufgebaut und die untere poröse Schicht weist eine zweite Dicke auf, die größer als die erste Dicke ist, und weist eine zweite Porosität auf, die größer als die erste Porosität ist.

公开(公告)号：GB2492444B

公开(公告)日：2013-08-14

申请号：GB201208147

申请日：2012-05-10

Applicant: IBM

Inventor： BEDELL STEPHEN ,  FOGEL KEITH ,  LAURO PAUL ,  CORTES NORMA EDITH SOSA ,  SHAHRJERDI DAVOOD ,  SADANA DEVENDRA

IPC: H01L31/18

公开(公告)号：DE112011100445T5

公开(公告)日：2013-04-04

申请号：DE112011100445

申请日：2011-02-01

Applicant: IBM

Inventor： BEDELL STEPHEN ,  SADANA DEVENDRA ,  FOGEL KEITH ,  VICHICONTI JAMES ,  KIM JEE HWAN ,  INNS DANIEL

IPC: H01L21/18

Abstract: Ein Verfahren für den Schichttransfer unter Verwendung einer mit Bor dotierten Silicium-Germanium(SiGe)-Schicht beinhaltet das Bilden einer mit Bor dotierten SiGe-Schicht auf einem Volumen-Silicium-Substrat; das Bilden einer oberen Silicium(Si)-Schicht über der mit Bor dotierten SiGe-Schicht; das Wasserstoffpassivieren der mit Bor dotierten SiGe-Schicht; das Verbinden der oberen Si-Schicht mit einem alternativen Substrat; und das Fortpflanzen einer Bruchstelle an einer Grenzfläche zwischen der mit Bor dotierten SiGe-Schicht und dem Volumen-Silicium-Substrat. Ein System für den Schichttransfer unter Verwendung einer mit Bor dotierten Silicium-Germanium(SiGe)-Schicht beinhaltet ein Volumen-Silicium-Substrat; eine auf dem Volumen-Silicium-Substrat gebildete, mit Bor dotierte SiGe-Schicht, so dass sich die mit Bor dotierte SiGe-Schicht unter einer oberen Silicium(Si)-Schicht befindet, wobei die mit Bor dotierte SiGe-Schicht so ausgebildet ist, dass sich nach Wasserstoffpassivieren der mit Bor dotierten SiGe-Schicht eine Bruchstelle an einer Grenzfläche zwischen der mit Bor dotierten SiGe-Schicht und dem Volumen-Silicium-Substrat fortpflanzt; und ein alternatives, mit der oberen Si-Schicht verbundenes Substrat.

公开(公告)号：AT552611T

公开(公告)日：2012-04-15

申请号：AT04703076

申请日：2004-01-16

Applicant: IBM

Inventor： CHEN HUAJIE ,  BEDELL STEPHEN ,  SADANA DEVENDRA ,  MOCUTA DAN

IPC: H01L21/331 ,  H01L21/02 ,  H01L21/20 ,  H01L21/205 ,  H01L21/316 ,  H01L21/762 ,  H01L21/84 ,  H01L29/10 ,  H01L29/786

Abstract: A method of forming a silicon germanium on insulator (SGOI) structure. A SiGe layer is deposited on an SOI wafer. Thermal mixing of the SiGe and Si layers is performed to form a thick SGOI with high relaxation and low stacking fault defect density. The SiGe layer is then thinned to a desired final thickness. The Ge concentration, the amount of relaxation, and stacking fault defect density are unchanged by the thinning process. A thin SGOI film is thus obtained with high relaxation and low stacking fault defect density. A layer of Si is then deposited on the thin SGOI wafer. The method of thinning includes low temperature (550° C.-700° C.) HIPOX or steam oxidation, in-situ HCl etching in an epitaxy chamber, or CMP. A rough SiGe surface resulting from HIPOX or steam oxidation thinning is smoothed with a touch-up CMP, in-situ hydrogen bake and SiGe buffer layer during strained Si deposition, or heating the wafer in a hydrogen environment with a mixture of gases HCl, DCS and GeH4.

公开(公告)号：AT368939T

公开(公告)日：2007-08-15

申请号：AT04809708

申请日：2004-09-10

Applicant: IBM

Inventor： BEDELL STEPHEN ,  CHOE KWANG SU ,  FOGEL KEITH ,  SADANA DEVENDRA

IPC: H01L21/762 ,  C22F1/10 ,  H01L21/20

Abstract: A simple and direct method of forming a SiGe-on-insulator that relies on the oxidation of a porous silicon layer (or region) that is created beneath a Ge-containing layer is provided. The method includes the steps of providing a structure comprising a Si-containing substrate having a hole-rich region formed therein and a Ge-containing layer atop the Si-containing substrate; converting the hole-rich region into a porous region; and annealing the structure including the porous region to provide a substantially relaxed SiGe-on-insulator material.

公开(公告)号：AU2020385351A1

公开(公告)日：2022-04-21

申请号：AU2020385351

申请日：2020-11-10

Applicant: IBM

Inventor： HOLMES STEVEN ,  SADANA DEVENDRA ,  HART SEAN ,  BEDELL STEPHEN ,  LI NING ,  GUMANN PATRYK

IPC: H01L39/02 ,  B82Y10/00 ,  G06N10/00 ,  H01L39/22 ,  H01L39/24

Abstract: A quantum computing device is fabricated by forming, on a superconductor layer (410), a first resist pattern defining a device region and a sensing region within the device region. The superconductor layer within the sensing region is removed, exposing a region of an underlying semiconductor layer (340) outside the device region. The exposed region of the semiconductor layer is implanted, forming an isolation region (240) surrounding the device region. Using an etching process subsequent to the implanting, the sensing region and a portion of the device region of the superconductor layer adjacent to the isolation region are exposed. By depositing a first metal layer within the sensing region, a tunnel junction gate (204) is formed. A sensing region gate (202) is formed by coupling the semiconductor layer with a second metal layer. A chemical potential gate (208, 210) is also formed. A nanorod contact (206, 212) using the second metal within the portion of the device region outside the sensing region is formed.