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    SRAM MEMORY CELL HAVING REDUCED SURFACE REGION
    11.
    发明专利
    SRAM MEMORY CELL HAVING REDUCED SURFACE REGION 失效

    公开(公告)号：JP2000200490A

    公开(公告)日：2000-07-18

    申请号：JP36405499

    申请日：1999-12-22

    Applicant: IBM

    Inventor： ELLIS-MONAGHAN JOHN J ,  WILBUR D PRISER

    IPC: G11C11/412 ,  H01L21/8244 ,  H01L27/11

    Abstract: PROBLEM TO BE SOLVED: To obtain a CMOS-SRAM having a reduced total number of transistors and a corresponding reduced surface region. SOLUTION: This cell has a pair of P channel transistor 22, 23 and a pair of N channel transistor 26, 27 connected as a bistable latch. A first common source connection part is connected to a write-in bit terminal, a residual source connection part is connected to a complementary bit line. A work line is given to a transistor connected to a bit line having contacts 22, 23 permitting read-out and write-in for a latch. At the time of a write-in mode, a work line is connected to a potential at which a transistor connected to a bit line is conducted, a write-in bit is connected to a potential at which residual transistors are made non-conductive. At the time of read operation, one of residual transistors is made to conduct and a work line conducts a pair of transistors connected to a bit line.

    FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE WITH MERGED SOURCE/DRAIN SILICIDE AND METHOD OF FORMING THE STRUCTURE
    13.
    发明申请
    FIN-TYPE FIELD EFFECT TRANSISTOR STRUCTURE WITH MERGED SOURCE/DRAIN SILICIDE AND METHOD OF FORMING THE STRUCTURE 审中-公开
    融合源/漏硅化物的FIN型场效应晶体管结构及形成结构的方法

    公开(公告)号：WO2009012295A3

    公开(公告)日：2009-03-12

    申请号：PCT/US2008070143

    申请日：2008-07-16

    Applicant: IBM ,  ANDERSON BRENT A ,  BRYANT ANDRES ,  ELLIS-MONAGHAN JOHN J ,  NOWAK EDWARD J

    Inventor： ANDERSON BRENT A ,  BRYANT ANDRES ,  ELLIS-MONAGHAN JOHN J ,  NOWAK EDWARD J

    IPC: H01L21/336

    CPC classification number: H01L29/785 ,  H01L29/41791 ,  H01L29/66795 ,  H01L2029/7858

    Abstract: Disclosed herein are embodiments of a multiple fin fin-type field effect transistor (350) (i.e., a multiple fin dual-gate or tri-gate field effect transistor) (300, 300a, 300b) in which the multiple fins arc partially or completely merged by a highly conductive material (360a, 360b) (e.g., a metal suicide). Merging the fins in this manner allow series resistance to be minimized with little, if any, increase in the parasitic capacitance between the gate and source/drain regions (375a-b). Merging the semiconductor fins (350) in this manner also allows each of the source/drain regions (375a-b) to be contacted by a single contact via as well as more flexible placement of that contact via.

    Abstract translation: 本文公开了多个鳍片式场效应晶体管（350）（即，多鳍式双栅极或三栅极场效应晶体管）（300,300a，300b）的实施例，其中多个鳍片部分地或完全地 由高导电材料（360a，360b）（例如金属硅化物）合并。 以这种方式合并鳍片允许串联电阻最小化，而栅极和源极/漏极区域（375a-b）之间的寄生电容几乎没有增加（如果有的话）。 以这种方式合并半导体鳍（350）还允许每个源极/漏极区（375a-b）通过单个接触通孔接触，以及该接触通孔更灵活的放置。

    METHOD FOR FORMING SELF-ALIGNED DUAL SALICIDE IN CMOS TECHNOLOGIES
    14.
    发明申请
    METHOD FOR FORMING SELF-ALIGNED DUAL SALICIDE IN CMOS TECHNOLOGIES 审中-公开
    在CMOS技术中形成自对准双重杀菌剂的方法

    公开(公告)号：WO2006060575A2

    公开(公告)日：2006-06-08

    申请号：PCT/US2005043474

    申请日：2005-12-01

    Applicant: IBM ,  CABRAL CYRIL JR ,  DZIOBKOWSKI CHESTER T ,  ELLIS-MONAGHAN JOHN J ,  FANG SUNFEI ,  LAVOIE CHRISTIAN ,  LUO ZHIJIONG ,  NAKOS JAMES S ,  STEEGEN AN L ,  WANN CLEMENT H

    Inventor： CABRAL CYRIL JR ,  DZIOBKOWSKI CHESTER T ,  ELLIS-MONAGHAN JOHN J ,  FANG SUNFEI ,  LAVOIE CHRISTIAN ,  LUO ZHIJIONG ,  NAKOS JAMES S ,  STEEGEN AN L ,  WANN CLEMENT H

    IPC: H01L21/8238 ,  H01L21/3205 ,  H01L21/44

    CPC classification number: H01L21/28518 ,  H01L21/823814 ,  H01L21/823835

    Abstract: A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region (103) in a semiconductor substrate (102) for accommodation of a first type semiconductor device (130); forming a second well region (104) in the semiconductor substrate (102) for accommodation of a second type semiconductor device (140); shielding the first type semiconductor device (130) with a mask (114); depositing a first metal layer (118) over the second type semiconductor device (140); performing a first salicide formation on the second type semiconductor device (140); removing the mask (114); depositing a second metal layer (123) over the first and second type semiconductor devices (130,140); and performing a second salicide formation on the first type semiconductor device (130). The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different suicide material over different devices.

    Abstract translation: 一种制造互补金属氧化物半导体（CMOS）器件的方法，其中所述方法包括在半导体衬底（102）中形成用于容纳第一类型半导体器件（130）的第一阱区（103）; 在所述半导体衬底（102）中形成用于容纳第二类型半导体器件（140）的第二阱区（104）; 用掩模（114）屏蔽所述第一类型半导体器件（130）; 在所述第二类型半导体器件（140）上沉积第一金属层（118）; 在所述第二类型半导体器件（140）上执行第一自对准硅化物形成; 去除所述面罩（114）; 在第一和第二类型半导体器件（130,140）上沉积第二金属层（123）; 以及在所述第一类型半导体器件（130）上执行第二自对准硅化物形成。 该方法仅需要一个图案级别，并且消除图案覆盖，因为它也简化了在不同设备上形成不同的自杀材料的过程。

    METHODS FOR FORMING ANTI-REFLECTION STRUCTURES FOR CMOS IMAGE SENSORS
    15.
    发明专利
    METHODS FOR FORMING ANTI-REFLECTION STRUCTURES FOR CMOS IMAGE SENSORS 未知

    公开(公告)号：CA2719681C

    公开(公告)日：2018-03-13

    申请号：CA2719681

    申请日：2009-05-05

    Applicant: IBM

    Inventor： ADKISSON JAMES W ,  ELLIS-MONAGHAN JOHN J ,  GAMBINO JEFFREY P ,  MUSANTE CHARLES F

    IPC: H01L31/18 ,  H01L21/77 ,  H01L27/146

    Abstract: Protuberances (5), having vertical (h) and lateral (p) dimensions less than the wavelength range of lights detectable by a photodiode (8), are formed at an optical interface between two layers having different refractive indices. The protuberances may be formed by employing self-assembling block copolymers that form an array of sub lithographic features of a first polymeric block component (112) within a matrix of a second polymeric block component (111). The pattern of the polymeric block component is transferred into a first optical layer (4) to form an array of nanoscale protuberances. Alternately, conventional lithography may be employed to form protuberances having dimensions less than the wavelength of light. A second optical layer is formed directly on the protuberances of the first optical layer. The interface between the first and second optical layers has a graded refractive index, and provides high transmission of light with little reflection.

    Silicium-auf-Isolator(SOI)-Struktur mit verringerten Oberschwingungen, Entwurfsstruktur und Verfahren zu deren Herstellung
    18.
    发明专利
    Silicium-auf-Isolator(SOI)-Struktur mit verringerten Oberschwingungen, Entwurfsstruktur und Verfahren zu deren Herstellung 未知

    公开(公告)号：DE112010004612T5

    公开(公告)日：2013-01-24

    申请号：DE112010004612

    申请日：2010-09-30

    Applicant: IBM

    Inventor： ELLIS-MONAGHAN JOHN J ,  LEVY MAX G ,  PHELPS RICHARD A ,  BOTULA ALAN B ,  JOSEPH ALVIN J ,  SLINKMAN JAMES A

    IPC: H01L27/12

    Abstract: Es wird eine Halbleiterstruktur (100) mit einer Isolatorschicht (120) auf einem Halbleitersubstrat (110) und einer Nutzschicht (130) auf der Isolatorschicht beschrieben. Das Substrat (110) ist mit einer relativ geringen Dosis eines Dotanden (111) eines bestimmten Leitungstyps dotiert, sodass es einen relativ hohen spezifischen Widerstand aufweist. Außerdem kann ein der Isolatorschicht unmittelbar benachbarter Teil (102) des Halbleitersubstrats mit einer geringfügig höheren Dosis desselben Dotanden (111), eines verschiedenen Dotanden (112) desselben Leitungstyps oder deren Kombination (111 und 112) dotiert werden. Wahlweise werden innerhalb desselben Teils (102) Mikrokavitäten (122, 123) erzeugt, um eine Erhöhung der Leitfähigkeit durch eine entsprechende Erhöhung des spezifischen Widerstands zu kompensieren. Durch die Erhöhung der Dotandenkonzentration an der Grenzfläche Halbleitersubstrat/Isolatorschicht steigt die Schwellenspannung (Vt) von entstehenden parasitären Kapazitäten an, wodurch das Oberschwingungsverhalten verringert wird. Ferner werden hierin auch Ausführungsformen eines Verfahrens und einer Entwurfsstruktur für eine solche Halbleiterstruktur beschrieben.

    SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS, DESIGN STRUCTURE AND METHOD
    19.
    发明专利
    SILICON-ON-INSULATOR (SOI) STRUCTURE CONFIGURED FOR REDUCED HARMONICS, DESIGN STRUCTURE AND METHOD 未知

    公开(公告)号：CA2780263A1

    公开(公告)日：2011-06-03

    申请号：CA2780263

    申请日：2010-09-30

    Applicant: IBM

    Inventor： BOTULA ALAN B ,  ELLIS-MONAGHAN JOHN J ,  JOSEPH ALVIN J ,  LEVY MAX G ,  PHELPS RICHARD A ,  SLINKMAN JAMES A

    IPC: H01L27/12

    Abstract: Disclosed is semiconductor structure (100) with an insulator layer (120) on a semiconductor substrate (110) and a device layer (130) is on the insulator layer. The substrate (110) is doped with a relatively low dose of a dopant (111) having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion (102) of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant (111), a different dopant (112) having the same conductivity type or a combination thereof (111 and 112). Optionally, micro-cavities (122, 123) are created within this same portion (102) so as to balance out any increase in conductivity with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method and a design structure for such a semiconductor structure.

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