公开(公告)号：MY125505A

公开(公告)日：2006-08-30

申请号：MYPI20004257

申请日：2000-09-13

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS D ,  HARAME DAVID L

IPC: H01L21/20 ,  H01L21/265 ,  H01L27/04 ,  H01L21/822 ,  H01L29/70 ,  H01L29/94

Abstract: A METHOD OF FORMING A DIFFUSION REGION IN A SILICON SUBSTRATE HAVING LOW-RESISTANCE, ACCEPTABLE DEFECT DENSITY, RELIABILITY AND PROCESS CONTROL COMPRISING THE STEPS OF : (a) SUBJECTING A SILICON SUBSTARE TO A FIRST ION IMPLANTATION STEP, SAID FIRST ION IMPLANTATION STEP BEING CONDUCTED UNDER CONDITIONS SUCH THAT A REGION OF AMORPHIZED Si IS FORMED IN SAID SILICON SUBSTRATE; (b) SUBJECTING SAID SILICON SUBSTRATE CONTAINING SAID REGION OF AMORPHIZED Si TO A SECOND ION IMPLANTATION STEP, SAID SECOND ION IMPLANTATION STEP BEING CARRIED OUT BY IMPLANTATION A DOPANT ION INTO SAID SILICON SUBSTRATE UNDER CONDITIONS SUCH THAT THE PEAK IF IMPLANT OF SAID DOPANT ION IS WITHIN THE REGION OF AMORPHIZED Si; AND (c) ANNEALING SAID SILICON SUBSTRATE UNDER CONDITIONS SUCH THAT SAID REGION OF AMORPHIZED Si IS RE-CRYSTALLIZED THEREBY FORMING A DIFFUSION REGION IN SAID SILICON SUBSTRATE IS PROVIDED.(FIG. 3C)

公开(公告)号：DE69231310D1

公开(公告)日：2000-09-07

申请号：DE69231310

申请日：1992-10-12

Applicant: IBM

Inventor： CRABBE EMMANUEL F ,  HARAME DAVID L ,  MEYERSON BERNARD S ,  PATTON GARY ,  STORK JOHANNES M C

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/165 ,  H01L29/737

Abstract: A heterojunction bipolar transistor having a single-crystal emitter with reduced charge storage and acceptable current gain is described herein. The heterojunction transistor comprises a collector region (604), a base region (606) formed on the collector region, and a single-crystal emitter region (608) grown on the base region (606) by low temperature epitaxy. During the formation of the base region (606), a graded profile of 5-23% germanium is added to the base, as the distance to the collector region (604) decreases, thereby decreasing the base bandgap as it approaches the collector region. Further, during the formation of the emitter region (608), a graded profile of 0-20% germanium is added to the emitter as the distance from the emitter-base junction increases. Thus, the emitter bandgap decreases as it moves farther from the emitter-base junction. The result of the above grading profiles is that the emitter bandgap is narrower at the emitter contact than the base bandgap at the emitter-base junction.

公开(公告)号：DE69014359T2

公开(公告)日：1995-05-24

申请号：DE69014359

申请日：1990-02-03

Applicant: IBM

Inventor： HARAME DAVID L ,  MEYERSON BERNHARD S ,  STORK JOHANNES M C

IPC: H01L29/73 ,  H01L21/20 ,  H01L21/331 ,  H01L21/74 ,  H01L21/8222 ,  H01L21/8228 ,  H01L21/8238 ,  H01L21/8249 ,  H01L27/06 ,  H01L29/08 ,  H01L21/314 ,  H01L21/265 ,  H01L29/70

公开(公告)号：DE112011101373B4

公开(公告)日：2015-12-31

申请号：DE112011101373

申请日：2011-05-17

Applicant: IBM

Inventor： JOSEPH ALVIN J ,  STRICKER ANDREAS D ,  HARAME DAVID L ,  DAHLSTROM MATTIAS E ,  GRAY PETER B ,  HERRIN RUSSELL T ,  CAMILLO-CASTILLO RENATA

IPC: H01L21/331 ,  H01L29/10 ,  H01L29/732 ,  H01L29/737

Abstract: Verfahren zur Bildung eines Transistors, aufweisend: Bilden einer intrinsischen Basisschicht (120) auf einer Oberseite eines Halbleitersubstrats (101); Bilden einer dielektrischen Schicht (130) auf der intrinsischen Basisschicht; Bilden einer extrinsischen Basisschicht (140) auf der dielektrischen Schicht; Bilden mindestens einer zweiten dielektrischen (302) Schicht auf der extrinsischen Basisschicht; Bilden einer Öffnung (315), die durch die mindestens eine zweite dielektrische Schicht zu der extrinsischen Basisschicht verläuft, wobei die Öffnung eine erste vertikale Seitenwand (306) aufweist; Bilden einer Seitenwand-Abstandsopferschicht (307) auf der ersten vertikalen Seitenwand; Bilden einer dielektrischen Opferschicht (309) auf einer freiliegenden Fläche der extrinsischen Basisschicht benachbart zu der Seitenwand-Abstandsopferschicht; selektives Entfernen der Seitenwand-Abstandsopferschicht; Bilden, zwischen der ersten vertikalen Seitenwand und der dielektrischen Opferschicht, eines Grabens (170), der durch die extrinsische Basisschicht und die erste dielektrische Schicht zu der intrinsischen Basisschicht verläuft, derart, dass der Graben an einen Umfang der Öffnung angepasst ist und eine zweite vertikale Seitenwand (175) aufweist, die direkt unter der ersten vertikalen Seitenwand mit dieser ausgerichtet ist; Bilden eines leitenden Streifens (150) innerhalb des Grabens benachbart zu der Seitenwand derart, dass der leitende Streifen die intrinsische Basisschicht mit der extrinsischen Basisschicht elektrisch verbindet; nach dem Bilden des leitenden Streifens, Bilden eines ersten Abschnitts (161) einer dielektrischen Abstandsschicht auf der ersten vertikalen Seitenwand (306), und der mindestens eine Oberseite des leitenden Streifens bedeckt; ...

公开(公告)号：DE112012004719T5

公开(公告)日：2014-08-07

申请号：DE112012004719

申请日：2012-08-14

Applicant: IBM

Inventor： HARAME DAVID L ,  STAMPER ANTHONY K

IPC: H03H9/54

Abstract: Es werden akustische Bulk-Wellen-Filter und/oder akustische Bulk-Resonatoren, die mit CMOS-Einheiten kombiniert sind, Verfahren zur Herstellung sowie eine Entwurfsstruktur bereitgestellt. Das Verfahren beinhaltet ein Bilden eines einkristallinen Trägers (18) aus einer Siliciumschicht (14) auf einem Isolator (12). Das Verfahren beinhaltet des Weiteren ein Bereitstellen einer Beschichtung aus einem Isolatormaterial (22) über dem einkristallinen Träger. Das Verfahren beinhaltet des Weiteren ein Bilden eines Durchkontakts (34a) durch das Isolatormaterial hindurch, wobei ein Wafer (10) freigelegt wird, der unter dem Isolator liegt. Das Isolatormaterial verbleibt über dem einkristallinen Träger. Das Verfahren beinhaltet des Weiteren ein Bereitstellen eines Opfermaterials (36) in dem Durchkontakt und über dem Isolatormaterial. Das Verfahren beinhaltet des Weiteren ein Bereitstellen einer Kappe (38) auf dem Opfermaterial. Das Verfahren beinhaltet des Weiteren ein Abführen des Opfermaterials und eines Anteils des Wafers unter dem einkristallinen Träger durch die Kappe hindurch, um einen oberen Hohlraum (42a) oberhalb des einkristallinen Trägers und einen unteren Hohlraum (42b) in dem Wafer unterhalb des einkristallinen Trägers zu bilden.

公开(公告)号：GB2494358B

公开(公告)日：2014-04-16

申请号：GB201300063

申请日：2011-05-17

Applicant: IBM

Inventor： CAMILLO-CASTILLO RENATA ,  DAHLSTROM MATTIAS E ,  GRAY PETER B ,  HARAME DAVID L ,  HERRIN RUSSELL T ,  JOSEPH ALVIN ,  STRICKER ANDREAS D

IPC: H01L29/06 ,  H01L21/331 ,  H01L29/10 ,  H01L29/66 ,  H01L29/732 ,  H01L29/737

Abstract: Disclosed are embodiments of a bipolar or heterojunction bipolar transistor and a method of forming the transistor. The transistor can incorporate a dielectric layer sandwiched between an intrinsic base layer and a raised extrinsic base layer to reduce collector-base capacitance Ccb, a sidewall-defined conductive strap for an intrinsic base layer to extrinsic base layer link-up region to reduce base resistance Rb and a dielectric spacer between the extrinsic base layer and an emitter layer to reduce base-emitter Cbe capacitance. The method allows for self-aligning of the emitter to base regions and incorporates the use of a sacrificial dielectric layer, which must be thick enough to withstand etch and cleaning processes and still remain intact to function as an etch stop layer when the conductive strap is subsequently formed. A chemically enhanced high pressure, low temperature oxidation (HIPOX) process can be used to form such a sacrificial dielectric layer.

公开(公告)号：GB2362508A

公开(公告)日：2001-11-21

申请号：GB0027232

申请日：2000-11-07

Applicant: IBM

Inventor： COOLBAUGH DOUGLAS D ,  DUNN JAMES S ,  GEISS PETER J ,  GRAY PETER B ,  HARAME DAVID L ,  SCHONENBERG KATHRYN T ,  ST ONGE STEPHEN A ,  SUBBANNA SESHADRI

IPC: H01L21/328 ,  H01L21/762 ,  H01L21/763 ,  H01L21/8222 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06

Abstract: A method of forming a semiconductor integrated circuit such as a BiCMOS integrated circuit comprises the steps of: (a) forming a first portion of a bipolar device in a first region of a substrate; (b) forming a first protective layer over the first region to protect the first portion of the bipolar devices; (c) forming field effect transistor devices in second regions of the substrate; (d) forming a second protective layer over the second regions of the substrate to protect the field effect transistor devices; (e) removing the first protective layer; (f) forming a second portion of the bipolar devices in the first region of the substrate; and (g) removing the second protective layer.

公开(公告)号：GB2509680A

公开(公告)日：2014-07-09

申请号：GB201408505

申请日：2012-08-14

Applicant: IBM

Inventor： HARAME DAVID L ,  STAMPER ANTHONY K

IPC: H03H3/02 ,  H03H9/10 ,  H03H9/17 ,  H03H9/56

Abstract: Bulk acoustic wave filters and/or bulk acoustic resonators integrated with CMOS devices, methods of manufacture and design structure are provided. The method includes forming a single crystalline beam (18) from a silicon layer (14) on an insulator (12). The method further includes providing a coating of insulator material (22) over the single crystalline beam. The method further includes forming a via (34a) through the insulator material exposing a wafer (10) underlying the insulator. The insulator material remains over the single crystalline beam. The method further includes providing a sacrificial material (36) in the via and over the insulator material. The method further includes providing a lid (38) on the sacrificial material. The method further includes venting, through the lid, the sacrificial material and a portion of the wafer under the single crystalline beam to form an upper cavity (42a) above the single crystalline beam and a lower cavity (42b) in the wafer, below the single crystalline beam.

公开(公告)号：GB2497177A

公开(公告)日：2013-06-05

申请号：GB201220384

申请日：2012-11-13

Applicant: IBM

Inventor： HARAME DAVID L ,  LIU QIZHI ,  PEKARIK JOHN JOSEPH ,  ELLIS-MONAGHAN JOHN JOSEPH ,  ADKISSON JAMES WILLIAM

IPC: H01L29/08 ,  H01L29/737

Abstract: A heterojunction bipolar transistor 100 and a method of forming the heterojunction bipolar transistor with a raised collector pedestal 125 in reduced dimension for reduced base-collector junction capacitance. The raised collector pedestal 125 is on the top surface of a substrate 121, 120, 101 and extends vertically through dielectric layer(s) 103, 104. The raised collector pedestal is un-doped or low-doped and is aligned above a sub-collector region 120, 121 contained within the substrate 101 and is narrower than that sub-collector region 120. An intrinsic base layer 105,132/131 is above the raised collector pedestal and the dielectric layer(s) 103, 104. An extrinsic base layer 141 is above the intrinsic base layer 132, 131. Thus, the space between the extrinsic base layer and the sub-collector region is increased. This increased space is filled by dielectric material and the electrical connection between the intrinsic base layer and the sub-collector region is provided by the relatively narrow, un-doped or low-doped, raised collector pedestal. Consequently the base-collector junction capacitance is reduced and the maximum oscillation frequency (fmax) is increased.

公开(公告)号：DE69231310T2

公开(公告)日：2001-02-15

申请号：DE69231310

申请日：1992-10-12

Applicant: IBM

Inventor： CRABBE EMMANUEL F ,  HARAME DAVID L ,  MEYERSON BERNARD S ,  PATTON GARY ,  STORK JOHANNES M C

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/165 ,  H01L29/737

Abstract: A heterojunction bipolar transistor having a single-crystal emitter with reduced charge storage and acceptable current gain is described herein. The heterojunction transistor comprises a collector region (604), a base region (606) formed on the collector region, and a single-crystal emitter region (608) grown on the base region (606) by low temperature epitaxy. During the formation of the base region (606), a graded profile of 5-23% germanium is added to the base, as the distance to the collector region (604) decreases, thereby decreasing the base bandgap as it approaches the collector region. Further, during the formation of the emitter region (608), a graded profile of 0-20% germanium is added to the emitter as the distance from the emitter-base junction increases. Thus, the emitter bandgap decreases as it moves farther from the emitter-base junction. The result of the above grading profiles is that the emitter bandgap is narrower at the emitter contact than the base bandgap at the emitter-base junction.