公开(公告)号：SG77263A1

公开(公告)日：2000-12-19

申请号：SG1999003754

申请日：1999-08-03

Applicant: IBM

Inventor： ASSADERAGHI FARIBORZ ,  MANDELMAN JACK ALLAN ,  HSU LOUIS L ,  GAMBINO JEFFREY PETER ,  BERTIN CLAUDE LOUIS

IPC: H01L21/336 ,  H01L21/8242 ,  H01L27/108 ,  H01L21/84 ,  H01L23/52 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L29/784

Abstract: An active FET body device which comprises an active FET region including a gate, a body region and electrical connection between said gate and said body region that is located within the active FET region is provided along with various methods for fabricating the devices. The electrical connection extends over substantially the entire width of the FET.

公开(公告)号：SG68008A1

公开(公告)日：1999-10-19

申请号：SG1997004577

申请日：1997-12-19

Applicant: IBM

Inventor： GAMBINO JEFFERY PETER ,  BRONNER GARY BELA ,  MANDELMAN JACK ALLAN ,  NESBIT LARRY ALAN

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8232 ,  H01L27/085

Abstract: A semiconductor MOSFET device is formed on a silicon substrate which includes trenches filled with Shallow Trench Isolation dielectric trench fill structures and extending above the surface of the substrate. The trench fill structures have protruding sidewalls with channel regions in the substrate having corner regions adjacent to the trench fill structures. The channel regions are between and adjacent to the STI trench fill structures doped with one concentration of dopant in the centers of the channel regions with a higher concentration of dopant in the corner regions. The dopant concentration differential provides a substantially equal concentration of electrons in the centers and at the corner regions of the channel regions.

公开(公告)号：JP2008010876A

公开(公告)日：2008-01-17

申请号：JP2007168478

申请日：2007-06-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MANDELMAN JACK ALLAN ,  BOOTH ROGER ALLEN JR ,  WILLIAM PAUL HOVIS

IPC: H01L29/78 ,  H01L29/786

CPC classification number: H01L29/7851 ,  H01L29/66795

Abstract: PROBLEM TO BE SOLVED: To provide a fin FET structure and its manufacturing method.
SOLUTION: The manufacturing method includes the steps for forming a silicon fin on the top surface of a bulk silicon substrate, forming gate dielectrics on the sidewalls at both sides of the fin, forming a gate electrode which comes into contact directly and physically with the gate dielectric layer on the sidewalls at both sides of the fin, forming a primary source/drain at a primary side fin in the channel region and forming a secondary source/drain at a secondary side fin in the channel region, removing a part of the bulk silicon substrate from the underside of at least one part of the primary and secondary source/drain regions for creating the void, and filling the void with the dielectric materials. The structure includes a body contact between a silicon body of the fin FET and the bulk silicon substrate.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供鳍式FET结构及其制造方法。 解决方案：制造方法包括在体硅衬底的顶表面上形成硅翅片的步骤，在翅片两侧的侧壁上形成栅极电介质，形成直接和物理接触的栅电极 在鳍的两侧的侧壁上具有栅介质层，在沟道区中的初级侧鳍形成初级源极/漏极，并在沟道区中的次级侧鳍形成次级源极/漏极，去除部分 从主源极/漏极区的至少一部分的下侧开始的体硅衬底产生空隙，并用电介质材料填充空隙。 该结构包括鳍状FET的硅体和体硅衬底之间的体接触。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2007158330A

公开(公告)日：2007-06-21

申请号：JP2006317786

申请日：2006-11-24

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MANDELMAN JACK ALLAN ,  LOUIS LU-CHEN HSU ,  YANG CHIH-CHAO ,  TONTI WILLIAM R

IPC: H01L21/82 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/04 ,  H01L27/06 ,  H01L27/08 ,  H01L29/786

CPC classification number: H01L23/5256 ,  H01L21/268 ,  H01L21/84 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor structure including at least one e-fuse, and a manufacturing method which is easily integrated with standard semiconductor technologies, thus minimizing implementation costs. SOLUTION: A semiconductor structure includes at least one e-fuse embedded in a trench that is located in a semiconductor substrate (a bulk or semiconductor-on-insulator substrate). According to the present invention, the e-fuse is in electrical contact with a dopant region that is located in the semiconductor substrate. The present invention also provides a method of manufacturing the semiconductor structure in which the embedded e-fuse and trench isolation regions are formed almost at the same time. COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供包括至少一个电熔丝的半导体结构和容易与标准半导体技术集成的制造方法，从而最小化实施成本。 解决方案：半导体结构包括嵌入在半导体衬底（主体或绝缘体上半导体衬底）上的沟槽中的至少一个电熔丝。 根据本发明，电熔丝与位于半导体衬底中的掺杂区电接触。 本发明还提供了一种制造半导体结构的方法，其中嵌入式电熔丝和沟槽隔离区几乎同时形成。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2000357749A

公开(公告)日：2000-12-26

申请号：JP2000160921

申请日：2000-05-30

Applicant: IBM

Inventor： MANDELMAN JACK ALLAN ,  BRONER GERI B ,  RAMACHANDRA DEIBAKARUNI

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/092 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a double work function doping and a borderless array diffusion contact. SOLUTION: This method includes steps for forming a semiconductor substrate 5, a gate insulator 10, conductors 61, 12 on the gate insulator, an insulation cap on the conductors, and an insulation spacer 92 on part of the sidewall of the conductors and of the insulation cap. This method also includes a step for doping a part of the semiconductor substrate and of the conductors with a first conductive dopant and the other part with a second conductive dopant. The conductors are annealed, to allow the first and the second conductive dopants to spread crossing into into each conductor.

公开(公告)号：JP2000058861A

公开(公告)日：2000-02-25

申请号：JP22482799

申请日：1999-08-09

Applicant: IBM

Inventor： ASSADERAGHI FARIBORZ ,  BERTIN CLAUDE L ,  GAMBINO JEFFREY P ,  HSU LOUIS LU-CHEN ,  MANDELMAN JACK ALLAN

IPC: H01L27/108 ,  H01L21/336 ,  H01L21/8242 ,  H01L21/84 ,  H01L23/52 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To obtain an active FET body device capable of balancing high-speed electric charges, decreasing off-current, and increasing on-current. SOLUTION: This embodiment comprises a silicon substrate 2, a silicon dioxide layer 3, a monocrystal silicon layer 4, a silicon dioxide layer 5, a spacer 13 of N+ doped polysilicon, a conformal layer 15 of a conductive diffusion preventing substance, a metal silicide layer 16, a CVD silicon dioxide layer 17, an insulator spacer 18, a silicon oxide layer 19, and a polysilicon 21. In an off-state, a gate contact with a body holds the body at a low word line level. In this state, a threshold takes a larger value. In addition to a voltage added to the N+ part 13 of a gate conductor, a potential from the body to a source rises. As a result, if the device is turned on, Vt lowers. By the effects of a dynamic Vt fall accompanied by a low off-current, this embodiment is suitable for a device using a very low voltage.

公开(公告)号：JP2000022100A

公开(公告)日：2000-01-21

申请号：JP13219499

申请日：1999-05-13

Applicant: IBM ,  SIEMENS AG

Inventor： HOENIGSCHMID HEINZ ,  HSU LOUIS LU-CHEN ,  MANDELMAN JACK ALLAN

IPC: H01L27/10 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a structure related to a semiconductor memory cell whose size is less than 4.5F2 in a case where F denotes the minimum dimension of a lithography techinique, and a manufacturing method thereof. SOLUTION: A semiconductor memory cell comprises a memory capacitor 12 formed in a trench, a transfer device formed in a mesa region which extends on the substantial arc of the periphery of the trench and is electrically isolated, and a buried strap which electrically connects the transfer device to the memory capacitors, wherein the transfer device comprises a controlled conduction channel located at a prescribed position on the arc removed from the buried strap.

公开(公告)号：JPH11289069A

公开(公告)日：1999-10-19

申请号：JP1527799

申请日：1999-01-25

Applicant: IBM

Inventor： HORAK DAVID VACLAV ,  FURUKAWA TOSHIHARU ,  HOLMES STEVEN JOHN ,  HAKEY MARK CHARLES ,  MA WILLIAM HSIOH-LIEN ,  MANDELMAN JACK ALLAN

IPC: H01L21/76 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To integrate a step move element adjacent to a deep trench capacitor by arranging an FET on one portion of the deep trench capacitor in a substrate, and providing an insulation region with a larger depth than the FET while surrounding the FET. SOLUTION: An FET is arranged on one portion of a deep trench capacitor 13 in a substrate, a travel element gate 17 is arranged on one portion of the deep trench capacitor 13 in the FET, and an n+ diffusion region 23 being separated from the travel element gate 17 by the insulation layer is formed adjacent to the side part of the travel element gate 17. Also, an isolation region 15 being insulated from the travel element gate 17 of the FET is arranged on one portion of the deep trench capacitor that is not covered with the FET, surrounds the FET and is located in the substrate, thus forming a larger depth than the FET and hence integrating the step travel element adjacent to the deep trench capacitor 13.

公开(公告)号：JPH10289980A

公开(公告)日：1998-10-27

申请号：JP9920098

申请日：1998-04-10

Applicant: IBM

Inventor： LOUIS RUU CHEN FUU ,  MANDELMAN JACK ALLAN ,  FARIBORTZ ATSUSADERAHI

IPC: G11C11/00 ,  H01L21/8242 ,  H01L21/8244 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To design a smart-card integrated circuit whose density is high, whose chip size is small and which is low-cost by a method wherein a semiconductor memory device which contains an NVRAM cell structure, a DRAM cell structure and an SRAM cell structure is formed on an identical substrate. SOLUTION: An NVRAM cell structure, a DRAM cell structure and an SRAM cell structure are formed on an identical substrate. In the NVRAM cell structure, a double polysilicon layer is used as the topology of a stacked capacitor DRAM and as a material layer, a staked capacitor is formed, and shallow trench isolation regions 26, 28 are formed on the substrate adjacent to a source region and a drain region inside the substrate. In the DRAM cell structure, a source region, a drain region and a trench isolation region 28 are contained, and a gate structure which is the same as in the VRAM cell structure and a stud interconnection are contained. In the SRAM cell structure, a source region and a drain region which are the same as in the NVRAM cell structure and the DRAM cell structure are contained, and a stud interconnection is contained.

公开(公告)号：JP2013123077A

公开(公告)日：2013-06-20

申请号：JP2013025314

申请日：2013-02-13

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Machines Corporation

Inventor： MANDELMAN JACK ALLAN ,  ROGER ALLEN BOOTH JR ,  WILLIAM PAUL HOVIS

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/7851 ,  H01L29/66795

Abstract: PROBLEM TO BE SOLVED: To provide a finFET structure and a method of fabricating the same.SOLUTION: The method includes: forming a silicon fin on a top surface of a bulk silicon substrate; forming a gate dielectric on opposite sidewalls of the fin; forming a gate electrode in direct physical contact with the gate dielectric layer on the opposite sidewalls of the fin; forming a first source/drain in the fin on a first side of a channel region and forming a second source/drain in the fin on a second side of the channel region; removing a portion of the bulk silicon substrate from under at least a portion of the first and second source/drains to create a void; and filling the void with a dielectric material. The structure includes a body contact between the silicon body of the finFET and the bulk silicon substrate.

Abstract translation: 要解决的问题：提供finFET结构及其制造方法。 解决方案：该方法包括：在体硅衬底的顶表面上形成硅翅片; 在翅片的相对侧壁上形成栅电介质; 形成与所述鳍片的相对侧壁上的栅极电介质层直接物理接触的栅电极; 在通道区域的第一侧上在所述鳍片中形成第一源极/漏极，并且在所述沟道区域的第二侧上在所述鳍片中形成第二源极/漏极; 从第一和第二源/排水沟的至少一部分下方去除体硅衬底的一部分以产生空隙; 并用介电材料填充空隙。 该结构包括在finFET的硅体和体硅衬底之间的体接触。 版权所有（C）2013，JPO＆INPIT