公开(公告)号：WO2005043614A3

公开(公告)日：2005-11-03

申请号：PCT/EP2004052704

申请日：2004-10-28

Applicant: IBM ,  IBM UK ,  CHEN TZE-CHIANG ,  COHEN GUY ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA ,  SHAHIDI GHAVAM

Inventor： CHEN TZE-CHIANG ,  COHEN GUY ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA ,  SHAHIDI GHAVAM

IPC: H01L21/762 ,  H01L27/12 ,  H01L27/144 ,  H01L31/0232 ,  H01L31/028 ,  H01L31/0352 ,  H01L31/105 ,  H01L31/18 ,  H01L21/265 ,  H01L21/306 ,  H01L21/324 ,  H01L27/14

CPC classification number: H01L21/76254 ,  H01L31/02327 ,  H01L31/028 ,  H01L31/1812 ,  Y02E10/547

Abstract: A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed.

Abstract translation: 提供了用于制造绝缘体上锗（GOI）衬底材料的方法，通过该方法制造的GOI衬底材料以及可以包括至少本发明的GOI衬底材料的各种结构。 GOI衬底材料至少包括衬底，位于衬底顶上的掩埋绝缘体层以及位于掩埋绝缘体层顶上的含Ge层，优选纯Ge。 在本发明的GOI基板材料中，含Ge层也可以被称为GOI膜。 GOI膜是其中可以形成器件的本发明衬底材料的层。

公开(公告)号：WO2009056478A2

公开(公告)日：2009-05-07

申请号：PCT/EP2008064272

申请日：2008-10-22

Applicant: IBM ,  BEDELL STEPHEN ,  DE SOUZA JOEL ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA

Inventor： BEDELL STEPHEN ,  DE SOUZA JOEL ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA

IPC: H01L21/762

CPC classification number: H01L21/76245 ,  H01L21/02126 ,  H01L21/022 ,  H01L21/02203 ,  H01L21/02236 ,  H01L21/02238 ,  H01L21/02258 ,  H01L21/02337 ,  H01L21/3167

Abstract: A method of fabricating a strained semiconductor-on- insulator (SSOI) substrate is provided. The method includes first providing a structure that includes a substrate, a doped and relaxed semiconductor layer on the substrate, and a strained semiconductor layer on the doped and relaxed semiconductor layer. In the invention, the doped and relaxed semiconductor layer having a lower lattice parameter than the substrate. Next, at least the doped and relaxed semiconductor layer is converted into a buried porous layer and the structure including the buried porous layer is annealed to provide a strained semiconductor-on-insulator substrate. During the annealing, the buried porous layer is converted into a buried oxide layer.

Abstract translation: 提供一种制造应变半导体绝缘体（SSOI）衬底的方法。 该方法包括首先提供包括衬底，衬底上的掺杂和弛豫半导体层以及掺杂和弛豫半导体层上的应变半导体层的结构。 在本发明中，掺杂和松弛的半导体层具有比衬底更低的晶格参数。 接下来，至少将掺杂和松弛的半导体层转换成掩埋多孔层，并且将包括埋入多孔层的结构退火以提供应变绝缘体上半导体衬底。 在退火过程中，将埋入的多孔层转化为掩埋氧化物层。

公开(公告)号：WO2006057645A3

公开(公告)日：2006-11-30

申请号：PCT/US2004042179

申请日：2004-12-15

Applicant: IBM ,  CHAN VICTOR ,  FISCHETTI MASSIMO V ,  HERGENROTHER JOHN M ,  LEONG MEIKEI ,  RENGARAJAN RAJESH ,  REZNICEK ALEXANDER ,  SOLOMON PAUL ,  SUNG CHUN-YUNG ,  YANG MIN

Inventor： CHAN VICTOR ,  FISCHETTI MASSIMO V ,  HERGENROTHER JOHN M ,  LEONG MEIKEI ,  RENGARAJAN RAJESH ,  REZNICEK ALEXANDER ,  SOLOMON PAUL ,  SUNG CHUN-YUNG ,  YANG MIN

IPC: H01L29/02 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/786 ,  H01L31/109

CPC classification number: H01L29/7842 ,  H01L21/823807 ,  H01L29/045 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/78684

Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a -containing layer having a 110 crystal orientation and a biaxial compressive strain. The term ''biaxial compressive stress'' is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing 110 layer; and creating a biaxial strain in the silicon-containing 110 layer.

公开(公告)号：WO2006057645A9

公开(公告)日：2006-09-14

申请号：PCT/US2004042179

申请日：2004-12-15

Applicant: IBM ,  CHAN VICTOR ,  FISCHETTI MASSIMO V ,  HERGENROTHER JOHN M ,  LEONG MEIKEI ,  RENGARAJAN RAJESH ,  REZNICEK ALEXANDER ,  SOLOMON PAUL ,  SUNG CHUN-YUNG ,  YANG MIN

Inventor： CHAN VICTOR ,  FISCHETTI MASSIMO V ,  HERGENROTHER JOHN M ,  LEONG MEIKEI ,  RENGARAJAN RAJESH ,  REZNICEK ALEXANDER ,  SOLOMON PAUL ,  SUNG CHUN-YUNG ,  YANG MIN

IPC: H01L29/02 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/786 ,  H01L31/109

CPC classification number: H01L29/7842 ,  H01L21/823807 ,  H01L29/045 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/78684

Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a -containing layer having a 110 crystal orientation and a biaxial compressive strain. The term ''biaxial compressive stress'' is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing 110 layer; and creating a biaxial strain in the silicon-containing 110 layer.

公开(公告)号：AU2021291163B2

公开(公告)日：2024-05-02

申请号：AU2021291163

申请日：2021-06-04

Applicant: IBM

Inventor： LI TAO ,  KANG TSUNG-SHENG ,  XIE RUILONG ,  REZNICEK ALEXANDER ,  GLUSCHENKOV OLEG

IPC: H01L27/088

Abstract: Semiconductor device designs having a buried power rail (602) with a sloped epitaxy buried contact (1702) are provided. In one aspect, a semiconductor FET device includes: at least one gate disposed on a substrate (202); source and drains (906) on opposite sides of the at least one gate, wherein at least one of the source and drains (906) has a sloped surface (1402); a buried power rail (602) embedded in the substrate (202); and a buried contact (1702) that connects the buried power rail (602) to the sloped surface (1402) of the at least one source and drain (906). Sidewall spacers (502) separate the buried power rail (602) from the substrate (202). A top of the sloped surface (1402) of the at least one source and drain (906) is above a top surface of the buried contact (1702).Methods of forming a semiconductor FET device are also provided.

公开(公告)号：AU2020389368A1

公开(公告)日：2022-04-21

申请号：AU2020389368

申请日：2020-10-23

Applicant: IBM

Inventor： REZNICEK ALEXANDER ,  RIZZOLO MICHAEL ,  XIE RUILONG

IPC: G11C11/16

Abstract: A memory cell is provided in which a bottom electrode of a magnetoresistive random access memory (MRAM) device is connected to one of the source/drain contact structure of a transistor, and a lower contact structure is connected to another of the source/drain contact structures of the transistor. In the present application, the MRAM device and the lower contact structure are present in the middle-of-the-line (MOL) not the back-end-of-the-line (BEOL). Moreover, the bottom electrode of the MRAM device, and a lower portion of the lower contact structure are present in a same dielectric material (i.e. a MOL dielectric material).

公开(公告)号：DE112020000931T5

公开(公告)日：2021-11-04

申请号：DE112020000931

申请日：2020-04-06

Applicant: IBM

Inventor： REZNICEK ALEXANDER ,  YAU JENG-BANG ,  HEKMATSHOARTABARI BAHMANN

IPC: G01N27/26 ,  G01N27/414 ,  G01N33/483 ,  H01L29/73

Abstract: Ein Biosensor enthält ein massives Silicium-Substrat und einen auf mindestens einem Teil des Substrats gebildeten vertikalen Transistor mit bipolarem Übergang (BJT). Der BJT enthält einen Emitter-Bereich, einen Kollektor-Bereich und einen epitaxial aufgewachsenen eigenleitenden Basis-Bereich zwischen dem Emitter-Bereich und dem Kollektor-Bereich. Ferner enthält der Biosensor eine auf mindestens einem Teil von zwei vertikalen Oberflächen des eigenleitenden Basis-Bereichs des BJT gebildete Sensorstruktur. Die Sensorstruktur enthält eine Kanal-Graben-Öffnung, die den eigenleitenden Basis-Bereich auf einer ersten und/oder einer zweiten einander gegenüberliegenden Seite freilegt, und mindestens eine in der Kanal/Graben-Öffnung gebildete dielektrische Schicht, die mit mindestens einem Teil des eigenleitenden Basis-Bereichs in Kontakt steht, wobei dielektrische Schicht in der Lage ist, auf Ladungen in biologischen Molekülen anzusprechen.

公开(公告)号：GB2511247B

公开(公告)日：2015-02-18

申请号：GB201410067

申请日：2012-08-07

Applicant: IBM

Inventor： CHENG KANGGUO ,  ADAM THOMAS N ,  KHAKIFIROOZ ALI ,  REZNICEK ALEXANDER

IPC: H01L29/94 ,  H01L21/84 ,  H01L27/12 ,  H01L29/861

公开(公告)号：DE602004024448D1

公开(公告)日：2010-01-14

申请号：DE602004024448

申请日：2004-12-15

Applicant: IBM

Inventor： CHAN VICTOR ,  FISCHETTI MASSIMO V ,  HERGENROTHER JOHN M ,  LEONG MEIKEI ,  RENGARAJAN RAJESH ,  REZNICEK ALEXANDER ,  SOLOMON PAUL ,  SUNG CHUN-YUNG ,  YANG MIN

IPC: H01L29/02 ,  H01L21/762 ,  H01L21/8238 ,  H01L29/04 ,  H01L29/786 ,  H01L31/109

Abstract: The present invention provides a semiconductor material that has enhanced electron and hole mobilities that comprises a Si-containing layer having a crystal orientation and a biaxial compressive strain. The term “biaxial compressive stress” is used herein to describe the net stress caused by longitudinal compressive stress and lateral stress that is induced upon the Si-containing layer during the manufacturing of the semiconductor material. Other aspect of the present invention relates to a method of forming the semiconductor material of the present invention. The method of the present invention includes the steps of providing a silicon-containing layer; and creating a biaxial strain in the silicon-containing layer.

公开(公告)号：DE112021005954B4

公开(公告)日：2024-11-28

申请号：DE112021005954

申请日：2021-10-28

Applicant: IBM

Inventor： XIE RUILONG ,  WANG JUNLI ,  LEE CHOONGHYUN ,  REZNICEK ALEXANDER

IPC: H01L23/535 ,  H01L21/336 ,  H01L21/768 ,  H01L29/165 ,  H01L29/78

Abstract: Halbleiterstruktur (200), aufweisend:eine vergrabene Stromversorgungsschiene (130) unter einer unteren Source-Drain (116) eines vertikalen Transistors;eine dielektrische Doppelschicht (124, 128) unter der unteren Source-Drain, wobei die dielektrische Doppelschicht (124, 128) zwischen der vergrabenen Stromversorgungsschiene (130) und der unteren Source-Drain (116) angeordnet ist;eine Silicium-Germanium-Doppelschicht (104, 106) unter der unteren Source-Drain (116), wobei die Silicium-Germanium-Doppelschicht (104, 106) zu der vergrabenen Stromversorgungsschiene (130) benachbart ist; undeinen Vergrabene-Stromversorgungsschiene-Kontakt, wobei der Vergrabene-Stromversorgungsschiene-Kontakt die untere Source-Drain (116) mit der vergrabenen Stromversorgungsschiene (130) verbindet.