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    REDUCTION OF TOPOGRAPHY BETWEEN SUPPORT REGIONS AND ARRAY REGIONS OF MEMORY DEVICES
    11.
    发明申请
    REDUCTION OF TOPOGRAPHY BETWEEN SUPPORT REGIONS AND ARRAY REGIONS OF MEMORY DEVICES 审中-公开
    支持区域和阵列区域之间的地理位置减少

    公开(公告)号：WO0199160A3

    公开(公告)日：2002-10-17

    申请号：PCT/US0119684

    申请日：2001-06-20

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： SCHNABEL RAINER FLORIAN ,  RADENS CARL J ,  LANDIS HOWARD ,  PARK YOUNG JIN ,  KOTECKI DAVID ,  REITH ARMIN M ,  TRICKLE WAYNE ,  WORDEMAN MATTHEW R

    IPC: H01L27/108

    CPC classification number: H01L27/10805 ,  H01L27/10808

    Abstract: A semiconductor memory device (100), in accordance with the present invention, includes a substrate having a major surface including an array region (102) and a support region (104). The array region includes memory cell structures (106) having a first height above the major surface of the substrate. The support area includes dummy structures (119) formed therein having a second height above the major surface. A dielectric layer (118) is formed over the memory cell structures in the array region and the dummy structures in the support region such that a top surface (122) of the dielectric layer is substantially planar wherein topographical features are substantially eliminated on the dielectric layer across the array region and the support region.

    Abstract translation: 根据本发明的半导体存储器件（100）包括具有包括阵列区域（102）和支撑区域（104）的主表面的衬底。 阵列区域包括在衬底的主表面上方具有第一高度的存储单元结构（106）。 支撑区域包括形成在其中的在主表面上方具有第二高度的虚拟结构（119）。 在阵列区域中的存储单元结构和支撑区域中的虚拟结构之间形成电介质层（118），使得电介质层的顶表面（122）基本上是平面的，其中在介电层上基本上消除了形貌特征 跨越阵列区域和支撑区域。

    METHOD OF PRODUCING TRENCH CAPACITOR BURIED STRAP
    12.
    发明申请
    METHOD OF PRODUCING TRENCH CAPACITOR BURIED STRAP 审中-公开
    生产TRENCH电容器BURIED STRAP的方法

    公开(公告)号：WO0201607A3

    公开(公告)日：2002-05-23

    申请号：PCT/US0120206

    申请日：2001-06-25

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  BERGNER WOLFGANG ,  BRONNER GARY B ,  GRUENING ULRIKE ,  KUDELKA STEPHEN ,  MICHAELIS ALEXANDER ,  NESBIT LARRY ,  RADENS CARL J ,  SCHLOESSER TILL ,  TEWS HEOMUT HORST

    IPC: H01L21/8242

    CPC classification number: H01L27/10864

    Abstract: A method for clearing an isolation collar (5) from a first interior surface of a deep trench at a location above a storage capacitor while leaving the isolation collar at other surfaces of the deep trench. A insulating material is deposited above a node conductor (3) of the storage capacitor. A layer of silicon (9) is deposited over the barrier material. Dopant ions are implanted at an angle (11) into the layer of deposited silicon within the deep trench, thereby leaving the deposited silicon unimplanted along one side of the deep trench. The unimplanted silicon is etched. The isolation collar is removed in locations previously covered by the unimplanted silicon, leaving the isolation collar in locations covered by the implanted silicon.

    Abstract translation: 一种用于在存储电容器上方的位置处从深沟槽的第一内表面清除隔离套环（5）的方法，同时将隔离套环留在深沟槽的其他表面。 绝缘材料沉积在存储电容器的节点导体（3）的上方。 一层硅（9）沉积在阻挡材料上。 将掺杂离子以角度（11）注入到深沟槽内的沉积硅层中，从而留下沉积的硅，沿着深沟槽的一侧不被植入。 未投影的硅被蚀刻。 隔离套环在先前被未投影硅覆盖的位置上移除，使隔离环位于植入硅覆盖的位置。

    CAPACITOR AND CAPACITOR CONTACT PROCESS FOR STACK CAPACITOR DRAMS
    13.
    发明申请
    CAPACITOR AND CAPACITOR CONTACT PROCESS FOR STACK CAPACITOR DRAMS 审中-公开
    电容器和电容接触过程用于堆叠电容器DRAMS

    公开(公告)号：WO0203423A3

    公开(公告)日：2002-08-08

    申请号：PCT/US0121164

    申请日：2001-07-02

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： DYER THOMAS W ,  KUNKEL GERHARD ,  HSU LOUIS L ,  LEE HEON ,  KOTECKI DAVID ,  LIMB YOUNG ,  RADENS CARL J ,  PARK YOUNG JIN

    IPC: H01L21/8242 ,  H01L23/528 ,  H01L23/532

    CPC classification number: H01L27/10852 ,  H01L23/5283 ,  H01L23/53228 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: A DRAM cell and method of fabrication are provided that eliminate critical photolithography fabrication steps by merging stacked capacitor formation with electrical contacts. The a single lithography step can be used to form the electrical contacts (28) because the stacked capacitors (46,48,50) are co-planar with the bit lines (36) and the stacked capacitors are located in the insulating material provided between the bit lines. Unlike conventional capacitor-over-bit line (COB) DRAM cells, this capacitor-beside-bit line DRAM cell eliminates the need to dedicate contacts to the capacitor, making it possible to achieve higher capacitance with lower global topography.

    Abstract translation: 提供了一种DRAM单元和制造方法，其通过将堆叠的电容器形成与电触点并入来消除关键的光刻制造步骤。 由于层叠的电容器（46,48,50）与位线（36）是共面的，所以单个光刻步骤可用于形成电触点（28），并且堆叠的电容器位于设置在 位线。 与常规的电容器位线（COB）DRAM单元不同，这种位线旁边的DRAM电池消除了将触点专用于电容器的需要，使得可以在较低的全局地形下实现更高的电容。

    15.
    发明专利
    未知

    公开(公告)号：DE10220542A1

    公开(公告)日：2002-12-05

    申请号：DE10220542

    申请日：2002-05-08

    Applicant: INFINEON TECHNOLOGIES CORP ,  IBM

    Inventor： RADENS CARL J ,  MANDELMAN JACK A ,  GRUENING ULRIKE

    IPC: H01L21/8242 ,  H01L27/02 ,  H01L27/108 ,  H01L29/94

    Abstract: A semiconductor device includes at least two active areas, each active area surrounding a corresponding trench in a substrate. The trenches each include a capacitor in a lower portion of the trench and a gate in an upper portion of the trench. A vertical transistor is formed adjacent to the trench in the upper portion for charging and discharging the capacitor. A body contact is formed between the at least two active areas. The body contact connects to the at least two active areas and to a diffusion well of the substrate for preventing floating body effects in the vertical transistor.

    PROCESS FOR MANUFACTURE OF TRENCH DRAM CAPACITOR BURIED PLATES
    18.
    发明专利
    PROCESS FOR MANUFACTURE OF TRENCH DRAM CAPACITOR BURIED PLATES 未知

    公开(公告)号：HK1032292A1

    公开(公告)日：2001-07-13

    申请号：HK01102673

    申请日：2001-04-17

    Applicant: IBM ,  INFINEON TECHNOLOGIES CORP

    Inventor： GRUENING ULRIKE ,  RADENS CARL J ,  TOBBEN DIRK

    IPC: H01L21/76 ,  H01L27/108 ,  H01L21/8242 ,  H01L

    Abstract: A process for manufacturing a deep trench capacitor in a trench (10). The capacitor comprises a collar (18) in an upper region of the trench and a buried plate (26) in a lower region of the trench. The improvement comprises, before forming the collar in the trench upper region, filling the trench lower region with a non-photosensitive underfill material (16) such as spin-on-glass. The process may comprise the steps of (a) forming a deep trench in a substrate; (b) filling the trench lower region with an underfill material; (c) forming a collar in the trench upper region; (d) removing the underfill; and (e) forming a buried plate in the trench lower region.

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