公开(公告)号：EP2313921A4

公开(公告)日：2014-08-27

申请号：EP09805365

申请日：2009-07-28

Applicant: IBM

Inventor： COLLINS DAVID S ,  JOSEPH ALVIN ,  LINDGREN PETER J ,  STAMPER ANTHONY K ,  WATSON KIMBALL M

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/522 ,  H01L23/481 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00012 ,  H01L2924/00

Abstract: An array of through substrate vias (TSVs) is formed through a semiconductor substrate and a contact-via-level dielectric layer thereupon. A metal-wire-level dielectric layer and a line-level metal wiring structure embedded therein are formed directly on the contact-via-level dielectric layer. The line-level metal wiring structure includes cheesing holes that are filled with isolated portions of the metal-wire-level dielectric layer. In one embodiment, the entirety of the cheesing holes is located outside the area of the array of the TSVs to maximize the contact area between the TSVs and the line-level metal wiring structure. In another embodiment, a set of cheesing holes overlying an entirety of seams in the array of TSVs is formed to prevent trapping of any plating solution in the seams of the TSVs during plating to prevent corrosion of the TSVs at the seams.

公开(公告)号：EP2250669A4

公开(公告)日：2012-07-25

申请号：EP09710899

申请日：2009-02-11

Applicant: IBM

Inventor： LINDGREN PETER J ,  SPROGIS EDMUND J ,  STAMPER ANTHONY K ,  STEIN KENNETH J

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A through substrate via includes an annular conductor layer at a periphery of a through substrate aperture, and a plug layer surrounded by the annular conductor layer. A method for fabricating the through substrate via includes forming a blind aperture within a substrate and successively forming and subsequently planarizing within the blind aperture a conformal conductor layer that does not fill the aperture and plug layer that does fill the aperture. The backside of the substrate may then be planarized to expose at least the planarized conformal conductor layer.

Abstract translation: 贯通基板通孔包括在通孔基板孔周边的环形导体层和由环形导体层包围的塞子层。 一种用于制造穿通基底通孔的方法，包括在基底内形成盲孔，并且在盲孔内依次形成并随后在盲孔内进行平坦化，该保形导体层不填充填充孔的孔和塞层。 然后可以将衬底的背面平坦化以至少露出平坦化的共形导体层。

公开(公告)号：JP2005203779A

公开(公告)日：2005-07-28

申请号：JP2005003396

申请日：2005-01-11

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： GAMBINO JEFFREY P ,  STAMPER ANTHONY K

IPC: H01L21/312 ,  H01L21/314 ,  H01L21/316 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76831 ,  H01L21/312 ,  H01L21/3121 ,  H01L21/3122 ,  H01L21/3148 ,  H01L21/31612 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76835 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a low-resistive interconnect structure on and in a rigid low-k interlayer dielectric layer.
SOLUTION: The method comprises the steps of providing a lower metal wiring layer having first metal lines 26 positioned within a lower low-k dielectric 32, depositing an upper low-k dielectric 6 on the lower metal wiring layer, etching at least one portion of the upper low-k dielectric to provide at least one via 24 to the first metal lines, forming rigid dielectric sidewall spacers 12 in at least one via of the upper low-k dielectric, and forming second metal lines 25 in at least one portion of the upper low-k dielectric.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种在刚性低k层间电介质层上和其中形成低电阻互连结构的方法。 解决方案：该方法包括以下步骤：提供具有位于下部低k电介质32内的第一金属线26的下金属布线层，在下金属布线层上沉积上部低k电介质6，至少蚀刻 上部低k电介质的一部分，以将至少一个通孔24提供给第一金属线，在上部低k电介质的至少一个通孔中形成刚性电介质侧壁间隔件12，并至少形成第二金属线25 上部低k电介质的一部分。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：EP2011208A4

公开(公告)日：2011-09-28

申请号：EP07759794

申请日：2007-03-30

Applicant: IBM

Inventor： HOOK TERENCE B ,  MOCUTA ANDA C ,  SLEIGHT JEFFREY W ,  STAMPER ANTHONY K

IPC: H02H9/00 ,  H01L27/02 ,  H01L27/12

CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0251 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1207

公开(公告)号：EP1766670A4

公开(公告)日：2011-03-02

申请号：EP05751777

申请日：2005-05-23

Applicant: IBM

Inventor： STAMPER ANTHONY K

IPC: H01L21/311 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L21/7682 ,  H01L21/31116 ,  H01L21/76807 ,  H01L28/87

公开(公告)号：EP1817801A4

公开(公告)日：2010-07-28

申请号：EP05851917

申请日：2005-11-18

Applicant: IBM

Inventor： ADKISSON JAMES W ,  GAMBINO JEFFREY P ,  JAFFE MARK D ,  LEIDY ROBERT K ,  STAMPER ANTHONY K

IPC: H01L31/062 ,  H01L21/00

CPC classification number: H01L27/14685 ,  H01L21/76819 ,  H01L21/76834 ,  H01L21/76838 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/14687

公开(公告)号：WO2007084982A8

公开(公告)日：2008-07-10

申请号：PCT/US2007060767

申请日：2007-01-19

Applicant: IBM ,  COOLBAUGH DOUGLAS D ,  DOWNES KEITH E ,  LINDGREN PETER J ,  STAMPER ANTHONY K

Inventor： COOLBAUGH DOUGLAS D ,  DOWNES KEITH E ,  LINDGREN PETER J ,  STAMPER ANTHONY K

IPC: H01L23/48

CPC classification number: H01L23/481 ,  H01L21/76808 ,  H01L21/76813 ,  H01L21/76832 ,  H01L23/5223 ,  H01L28/60 ,  H01L2221/1036 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method and semiconductor device. In the method, at least one partial via (26) is etched in a stacked structure and a border (32) is formed about the at least one partial via (26). The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer (22).

Abstract translation: 一种方法和半导体器件。 在该方法中，至少一个部分通孔（26）以堆叠结构被蚀刻，并且围绕至少一个部分通孔（26）形成边界（32）。 该方法还包括使用选择性蚀刻执行厚布线，同时继续蚀刻至少一个蚀刻停止层（22）。

公开(公告)号：JP2001308184A

公开(公告)日：2001-11-02

申请号：JP2001070270

申请日：2001-03-13

Applicant: IBM

Inventor： JONATHAN D CHAPPURUSOKORU ,  IVERS THOMAS H ,  MCGAHAY VINCENT J ,  STAMPER ANTHONY K

IPC: H01L23/522 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52

Abstract: PROBLEM TO BE SOLVED: To provide a shielded interconnection for reducing capacitive coupling between interconnecting lines in an integrated circuit device having interconnecting lines isolated by an interlayer dielectric. SOLUTION: Interconnecting lines are provided with a thin side wall conductive shield isolated from interconnecting lines by a thin side wall dielectric. Crosstalk between adjacent lines in an interconnection layer is reduced by a side wall shield. The thin side wall dielectric material can be selected to reduce capacitance between the side wall shield and the interconnecting lines. An interlayer dielectric can be selected to enhance defect resistance and mechanical strength during fabrication of a device. A method for fabricating shielded interconnections is also provided.

公开(公告)号：JP2001308100A

公开(公告)日：2001-11-02

申请号：JP2001077127

申请日：2001-03-16

Applicant: IBM

Inventor： ELLIS-MONAGHAN JOHN J ,  FEENEY PAUL M ,  ROBERT M JEFFKEN ,  LANDIS HOWARD S ,  PREVITI-KELLY ROSEMARY A ,  BERGMAN-REUTER BETTE L ,  RUTTEN MATTHEW J ,  STAMPER ANTHONY K ,  YANKEE SALLY J

IPC: H01L23/52 ,  H01L21/3205 ,  H01L21/60 ,  H01L21/768 ,  H01L23/31 ,  H01L23/485 ,  H01L23/532

Abstract: PROBLEM TO BE SOLVED: To provide means for making an ultra-low k dielectric material which is compatible with a C4/wire bond structure. SOLUTION: The manufacturing method and structure of a semiconductor chip comprises a plurality of interconnecting metallization layers, at least one deformable dielectric material layer covering the interconnecting metallization layers, at least one I/O bonding pad, and a support structure including a fairly rigid dielectric in supporting relation with the pads and avoiding crushing of the deformable dielectric material layer.

公开(公告)号：WO2007115146B1

公开(公告)日：2008-06-05

申请号：PCT/US2007065604

申请日：2007-03-30

Applicant: IBM ,  HOOK TERENCE B ,  MOCUTA ANDA C ,  SLEIGHT JEFFREY W ,  STAMPER ANTHONY K

Inventor： HOOK TERENCE B ,  MOCUTA ANDA C ,  SLEIGHT JEFFREY W ,  STAMPER ANTHONY K

IPC: H02H9/00

CPC classification number: H01L21/84 ,  H01L21/823807 ,  H01L21/823878 ,  H01L27/0251 ,  H01L27/0629 ,  H01L27/1203 ,  H01L27/1207

Abstract: A chip includes a CMOS structure having a bulk device (20) disposed in a first region (24) of a semiconductor substrate (50) in conductive communication with an underlying bulk region (18) of the substrate, the first region (24) and the bulk region (20) having a first crystal orientation. A SOI device (10) is disposed in a semiconductor-on-insulator ("SOI") layer (14) separated from the bulk region of the substrate by a buried dielectric layer (16), the SOI layer having a different crystal orientation from the first crystal orientation. In one example, the bulk device includes a p-type field effect transistor ("PFET") and the SOI device includes an n-type field effect transistor ("NFET") device. Alternatively, the bulk device can include an NFET and the SOI device can include a PFET. When the SOI device has a gate conductor (11) in conductive communication with a gate conductor (21) of the bulk device, charging damage can occur to the SOI device, except for the presence of diodes in reverse-biased conductive communication with the bulk region. The diodes are operable to conduct a discharge current to the bulk region when either a voltage on the gate conductor or a voltage on the source or drain region of the SOI device exceeds a diode's breakdown voltage.

Abstract translation: 芯片包括CMOS结构，其具有设置在半导体衬底（50）的第一区域（24）中的本体器件（20），该半导体衬底（50）与衬底的下面的体区域（18）导通连通，第一区域（24）和 本体区域（20）具有第一晶体取向。 SOI器件（10）通过埋入介质层（16）设置在与衬底的本体区域分离的绝缘体上半导体（“SOI”）层14中，SOI层具有不同的晶体取向 第一个晶体取向。 在一个示例中，体器件包括p型场效应晶体管（“PFET”），并且SOI器件包括n型场效应晶体管（“NFET”）器件。 或者，体器件可以包括NFET，并且SOI器件可以包括PFET。 当SOI器件具有与本体器件的栅极导体（21）导电连通的栅极导体（11）时，SOI器件可能会发生充电损坏，除了存在与体积反向偏置导电连通的二极管 地区。 当栅极导体上的电压或SOI器件的源极或漏极区域上的电压超过二极管的击穿电压时，二极管可操作以将放电电流传导到体区。