公开(公告)号：DE10111989C2

公开(公告)日：2003-11-06

申请号：DE10111989

申请日：2001-03-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KRIZ JAKOB ,  GRATZ ACHIM ,  POLEI VERONIKA ,  SPERL IRENE ,  RUDER THOMAS

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/485 ,  H01L23/60

公开(公告)号：DE102007043709A1

公开(公告)日：2008-04-03

申请号：DE102007043709

申请日：2007-09-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CHUNG WOONG-JAE ,  GRATZ ACHIM ,  KRIZ JAKOB

IPC: H01L23/52 ,  H01L21/768

Abstract: A via structure is disclosed for use in a multi-layered semiconductor device, for forming electrical contacts between prescribed layers of the vertically aligned structures. The via structures include a plurality of adjacent frame shaped hole structures which extend between the prescribed layers of the device, and which are filled with metal to form frame shaped vias. The width of each of the sides of the frame is chosen to be equal to an integer multiple of half of the minimum pitch of the semiconductor processing, with the distance between adjacent frame shaped via structures being approximately equal to an integer multiple of half of the minimum pitch of the semiconductor processing.

公开(公告)号：DE10355561A1

公开(公告)日：2005-06-30

申请号：DE10355561

申请日：2003-11-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEZI RECAI ,  WALTER ANDREAS ,  ENGL REIMUND ,  MALTENBERGER ANNA ,  DEHM CHRISTINE ,  ARKALGUD SITARAM ,  KASKO IGOR ,  NUETZEL JOACHIM ,  KRIZ JAKOB ,  MIKOLAJICK THOMAS ,  PINNOW CARL-UWE

IPC: C09D5/24 ,  C09D5/25 ,  G11C13/02 ,  H01L27/24 ,  H01L27/28 ,  H01L51/00 ,  H01L51/30

公开(公告)号：BR0113164A

公开(公告)日：2003-06-24

申请号：BR0113164

申请日：2001-08-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PALM HERBERT ,  WILLER JOSEF ,  GRATZ ACHIM ,  KRIZ JAKOB ,  ROEHRICH MAYK

IPC: H01L21/8247 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: Each memory cell is a memory transistor which is provided on a top side of a semiconductor body and has a gate electrode which is arranged in a trench located between a source region and a drain region that are formed in the semiconductor material. The gate electrode is separated from the semiconductor material by a dielectric material. At least between the source region and the gate electrode and between the drain region and the gate electrode, there is an oxide-nitride-oxide layer sequence. The layer sequence is provided for the purpose of trapping charge carriers at the source and the drain.

公开(公告)号：DE10134089A1

公开(公告)日：2003-01-30

申请号：DE10134089

申请日：2001-07-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SECK MARTIN ,  TILKE ARMIN ,  KRIZ JAKOB

IPC: H01L21/225 ,  H01L21/331 ,  H01L29/73 ,  H01L29/732 ,  H01L29/737

Abstract: The invention relates to a method for producing a bipolar transistor comprising a polysilicon emitter, according to which a collector region of a first conductivity type and an adjacent base region of a second conductivity type are created. At least one layer consisting of an insulating material is then applied, said layer or layers being structured in such a way that at least one section of the base region is exposed. A layer consisting of a polycrystalline semiconductor material of the first conductivity type, which is highly doped with doping atoms, is subsequently created, in such a way that the exposed section is essentially covered. A second layer consisting of a highly conductive material is then created on the layer consisting of the polycrystalline semiconductor material, forming a dual-layer emitter with the latter. At least one portion of the doping atoms of the first conductivity type of the highly doped polycrystalline semiconductor layer is then caused to diffuse into the base region, to create an emitter region of the first conductivity type.

公开(公告)号：DE10111989A1

公开(公告)日：2002-10-02

申请号：DE10111989

申请日：2001-03-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KRIZ JAKOB ,  GRATZ ACHIM ,  POLEI VERONIKA ,  SPERL IRENE ,  RUDER THOMAS

IPC: H01L21/02 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/485 ,  H01L23/60

Abstract: Process for reducing a plasma-induced charge in a semiconductor circuit having a support material (1), an electrically conducting layer (2), an auxiliary layer (3), an insulating layer (4) and a mask layer (5) comprises: removing the insulating layer using a plasma-promoted dry chemical method up to a minimum thickness using the mask layer; wet chemically removing the remaining insulating layer (R) up to the auxiliary layer using the mask layer; removing the mask layer; and wet chemically removing the auxiliary layer using the insulating layer as mask. Preferred Features: The insulating layer comprises an oxide layer and an oxynitride or nitride layer. The wet chemical removal step uses a hot aqueous solution having a high concentration of hydrogen super oxide.