公开(公告)号：DE59704333D1

公开(公告)日：2001-09-20

申请号：DE59704333

申请日：1997-11-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HOFMANN FRANZ ,  WILLER JOSEF ,  REISINGER HANS ,  VON BASSE PAUL-WERNER ,  KRAUTSCHNEIDER WOLFGANG

IPC: H01L21/28 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11568 ,  H01L29/788 ,  H01L29/792

Abstract: A number of memory cell lines insulated from one another and that respectively comprise a first doped region and a second doped region between which a gate dielectric, which contains a material with charge carrier traps and a number of gate electrodes. The spacing of neighboring gate electrodes is smaller than the dimensions of the gate electrodes. The information is stored by introduction of charge carriers into the gate dielectric. The gate electrodes are preferably manufactured with the assistance of a spacer technique.

公开(公告)号：DE19947117A1

公开(公告)日：2001-04-12

申请号：DE19947117

申请日：1999-09-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： STENGL REINHARD ,  REISINGER HANS ,  HANEDER THOMAS ,  BACHHOFER HARALD

IPC: H01L21/8247 ,  H01L21/8246 ,  H01L27/105 ,  H01L29/51 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  G11C11/22

Abstract: According to the invention, a first source-drain region (121), a channel region (13) and a second source-drain region (122) are located in a semiconductor substrate (11). A dielectric layer (14) covers at least the surface of the channel region and parts of the first source-drain region. On the surface of said dielectric layer, a ferroelectric layer (17) is provided between two polarization electrodes (16, 18). A gate electrode is positioned on the surface of the dielectric layer. The thickness of the dielectric layer is measured in such a way that a remanent polarization of the ferroelectric layer which is aligned between the two polarization electrodes, generates compensation charges in one section of the channel region. The ferroelectric transistor is suitable for use a memory cell in a memory cell arrangement.

公开(公告)号：DE19821901C2

公开(公告)日：2002-05-08

申请号：DE19821901

申请日：1998-05-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： REISINGER HANS ,  STENGL REINHARD ,  GRUENING ULRIKE ,  LEHMANN VOLKER ,  WENDT HERMANN ,  WILLER JOSEF ,  FRANOSCH MARTIN ,  SCHAEFER HERBERT

IPC: H01L21/8244 ,  H01L27/11 ,  G11C11/412

Abstract: An integrated electrical circuit has at least one memory cell, in which the memory cell is disposed in the region of a surface of a semiconductor substrate. The memory cell contains at least two inverters that are electrically connected to one another. The inverters each contain two complementary MOS transistors having a source, a drain and a channel, the channels of the complementary MOS transistors having different conductivity types. According to the invention, the integrated electrical circuit is constructed in such a way that the inverters are disposed perpendicularly to the surface of the semiconductor substrate. The source, the drain and the channel of the complementary MOS transistors are formed by layers which lie one on top of the other and are disposed in such a way that the complementary MOS transistors are situated one above the other. The invention furthermore relates to a method for fabricating the integrated electrical circuit.

公开(公告)号：DE10004392A1

公开(公告)日：2001-08-16

申请号：DE10004392

申请日：2000-02-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： REISINGER HANS ,  STEINLESBERGER GERNOT ,  HANEDER THOMAS ,  BACHHOFER HARALD

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/792 ,  H01L29/772

Abstract: A source/drain voltage is applied to the field effect transistor during injection of the charge carriers in the channel area of the field effect transistor with the purpose of achieving inhomogeneous distribution of the charge carrier in the channel area.

公开(公告)号：DE59814458D1

公开(公告)日：2010-08-26

申请号：DE59814458

申请日：1998-08-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KLOSE HELMUT ,  LEHMANN VOLKER ,  REISINGER HANS ,  HOENLEIN WOLFGANG

IPC: H01L27/04 ,  H01L27/108 ,  H01L21/3205 ,  H01L21/822 ,  H01L21/8242

公开(公告)号：DE59712601D1

公开(公告)日：2006-05-11

申请号：DE59712601

申请日：1997-07-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： REISINGER HANS ,  STENGL REINHARD ,  GRUENING ULRIKE ,  WENDT HERMANN ,  WILLER JOSEF ,  LEHMANN VOLKER ,  FRANOSCH MARTIN ,  SCHAEFER HERBERT ,  KRAUTSCHNEIDER WOLFGANG ,  HOFMANN FRANZ

IPC: H01L21/8247 ,  H01L29/792 ,  H01L27/115 ,  H01L29/51 ,  H01L29/788

Abstract: The invention concerns a non-volatile storage cell having a MOS transistor which, as gate dielectric, comprises a triple dielectric layer (5) consisting of a first silicon oxide layer (51), a silicon nitride layer (52) and a second silicon oxide layer (53). The MOS transistor gate electrode comprises p -doped silicon such that, when a negative voltage is applied to the gate electrode, holes tunnel predominantly from the channel area (4) through the first silicon oxide layer (51) and into the silicon nitride layer (52).

公开(公告)号：DE10324081B4

公开(公告)日：2005-11-17

申请号：DE10324081

申请日：2003-05-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： REISINGER HANS ,  STENGL REINHARD ,  SCHAEFER HERBERT

IPC: G11C13/02 ,  H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L51/00 ,  H01L51/30 ,  G11C11/21 ,  G11C19/00 ,  H01L21/762

公开(公告)号：DE10344039A1

公开(公告)日：2005-04-14

申请号：DE10344039

申请日：2003-09-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： REISINGER HANS ,  GUTSCHE MARTIN ,  SEIDL HARALD ,  GORDON ROY

IPC: H01L21/28 ,  H01L27/115 ,  H01L29/51 ,  H01L29/792

Abstract: An electrically programmable non-volatile memory based on threshold-changing MOSFETs comprises a charge-storing layer made from a compound of the formula: HfO xN y. An independent claim is also included for the production of an electrically programmable non-volatile memory based on threshold-changing MOSFETs.

公开(公告)号：DE59906526D1

公开(公告)日：2003-09-11

申请号：DE59906526

申请日：1999-05-03

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LEHMANN VOLKER ,  REISINGER HANS ,  WENDT HERMANN ,  STENGL REINHARD ,  LANGE GERRIT ,  OTTOW STEFAN

IPC: C25F3/12 ,  C25F3/02 ,  H01P1/20

Abstract: A substrate made from silicon has a first region and a second region. Through pores are formed in the first region. Pores that do not traverse the substrate are provided in the second region. The production of the work piece is performed with the aid of electrochemical etching of the pores. The entire surface of the substrate is covered with a mask layer that is structured photolithographically on the rear of the substrate. The bottoms of the pores in the second region are etched clear, preferably using KOH.

公开(公告)号：DE10324081A1

公开(公告)日：2004-12-23

申请号：DE10324081

申请日：2003-05-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： REISINGER HANS ,  STENGL REINHARD ,  SCHAEFER HERBERT

IPC: G11C13/02 ,  H01L21/02 ,  H01L21/8242 ,  H01L27/108 ,  H01L51/00 ,  H01L51/30 ,  G11C11/21 ,  G11C19/00 ,  H01L21/762

Abstract: The memory includes tubes (301) on the electrode layer (202) and in contact with it. A dielectric coating (302) covers them. Filler (403) intervenes in the spaces between them, and is connected to an opposite electrode (402). The configuration forms an electrical capacitor between the electrode layer and the opposite electrode, for charge storage. An independent claim is included for the method of manufacture.