11.
    发明专利
    未知

    公开(公告)号:DE19941148A1

    公开(公告)日:2001-04-19

    申请号:DE19941148

    申请日:1999-08-30

    Abstract: A memory having a memory cell formed in a substrate and including a trench capacitor and a transistor and a method for producing the memory includes connecting the trench capacitor to the transistor with a self-aligned connection. The transistor at least partly covers the trench capacitor. The trench capacitor is filled with a conductive trench filling and an insulating covering layer is situated on the conductive trench filling. An epitaxial layer is situated above the insulating covering layer. The transistor is formed in the epitaxial layer. The self-aligned connection is formed in a contact trench and includes an insulation collar in which a conductive material is introduced. A conductive cap is formed on the conductive material.

    13.
    发明专利
    未知

    公开(公告)号:DE50011386D1

    公开(公告)日:2006-03-02

    申请号:DE50011386

    申请日:2000-06-06

    Abstract: A non-volatile semiconductor memory cell and an associated method are disclosed, in which a conventional dielectric ONO layer (10) is replaced by a very thin metal oxide layer (6) of WOx and/or TiO2. The high relative dielectric constant of these materials further improves the integration density and the control voltages required for the semiconductor memory cell.

    14.
    发明专利
    未知

    公开(公告)号:DE10146888C1

    公开(公告)日:2003-04-10

    申请号:DE10146888

    申请日:2001-09-24

    Abstract: To fabricate a trench capacitor in a substrate, a trench is formed in the substrate. The trench has an upper region and a lower region. In the trench, first of all nanocrystallites and/or a seed layer for nanocrystallites are deposited in the upper region and the lower region. Then, the nanocrystallites and/or the seed layer are removed from the upper region of the trench by means of an etching process. The etching parameters of the etching process are selected in such a way that the seed layer and/or the nanocrystallites which are uncovered in the upper region and the lower region are removed only from the upper region. Consequently, an expensive mask layer can be avoided in the lower region of the trench.

    16.
    发明专利
    未知

    公开(公告)号:DE19944012A1

    公开(公告)日:2001-03-22

    申请号:DE19944012

    申请日:1999-09-14

    Inventor: SCHREMS MARTIN

    Abstract: The invention relates to a trench capacitor (160) for use in a semiconductor memory cell (100). The trench capacitor (160) is formed in a substrate (101) and comprises: a trench (108) with an upper region (109) and a lower region (110); an insulation collar (168) which is formed in the upper region (109) on a trench wall of the trench (108); a buried trough (170) through which the lower region (110) of the trench (108) at least partial extends; a conductive layer (310) which serves as an outer capacitor electrode and which is provided for covering the lower region (110) of the trench (108) and of the insulation collar (168); a dielectric layer (164) which is provided for covering the conductive layer (310) and which serves as a capacitor dielectric, and; a conductive trench filling (161) with which the trench (108) is filled and which serves as an inner capacitor electrode.

    18.
    发明专利
    未知

    公开(公告)号:DE10147894B4

    公开(公告)日:2007-08-23

    申请号:DE10147894

    申请日:2001-09-28

    Abstract: An integrated semiconductor circuit is fabricated by bringing substrate as electrode into contact with electrolysis liquid and carrying out electrolysis, so as to selectively grow material on inner wall of the recess while the insulating layer prevents the material from growing outside the recess, and convert the reserve material into the material that is grown by electrolysis. Fabrication of integrated semiconductor circuit comprises forming recess or recesses in a surface of a semiconductor substrate (2), epitaxially depositing a reserve material on an inner wall (4) of the recess, producing an electrically insulating layer (6) on the surface of the substrate outside the recess. The substrate is brought as electrode into contact with an electrolysis liquid (7) and electrolysis is performed, so as to selectively grow the material on the inner wall of the recess while the insulating layer prevents the material from growing outside the recess, and convert the reserve material into the material that is grown by electrolysis.

    Storage cell used as a DRAM storage cell comprises a substrate, a trench arranged in the substrate, an insulation collar arranged in the middle region of the trench, a dielectric layer

    公开(公告)号:DE10111499C1

    公开(公告)日:2002-07-11

    申请号:DE10111499

    申请日:2001-03-09

    Abstract: Storage cell comprises a substrate (2); a trench (3) having a lower region, a middle region, an upper region and an inner wall arranged in the substrate; an insulation collar (8) arranged in the middle region on the inner wall of the trench; a dielectric layer (9) arranged in the lower region of the trench; a conducting trench filling (10) arranged in the lower region and the middle region of the trench; an epitaxially grown layer (11) arranged in the upper region of the trench on the inner wall; and a barrier layer (60) arranged between the filling and the epitaxially grown layer. An Independent claim is also included for a process for the production of the storage cell. Preferred Features: A second dielectric layer with an inner opening is arranged in the upper region of the trench above the epitaxially grown layer. A second trench is arranged in the epitaxially grown layer.

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