公开(公告)号：FR2979033A1

公开(公告)日：2013-02-15

申请号：FR1202206

申请日：2012-08-08

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BERGER RUDOLF ,  GRUBER HERMANN ,  LEHNERT WOLFGANG ,  RUHL GUENTHER ,  FOERG RAIMUND ,  MAUDER ANTON ,  SCHULZE HANS JOACHIM ,  KELLERMANN KARSTEN ,  SOMMER MICHAEL ,  ROTTMAIR CHRISTIAN ,  RUPP ROLAND

IPC: H01L21/71 ,  H01L21/20 ,  H01L21/48 ,  H01L23/14

Abstract: Procédé de fabrication d'une tranche (13) composite, on se procure une tranche de support comprenant une couche de graphite, on se procure une tranche (10) semiconductrice monocristalline ayant une première face (11) et une deuxième face (12) ; et on forme une couche de liaison sur au moins l'une de la première face (11) de la tranche semiconductrice et de la couche de graphite de la tranche de support.

公开(公告)号：DE102009022153A1

公开(公告)日：2009-12-31

申请号：DE102009022153

申请日：2009-05-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SOMMER MICHAEL

IPC: H01L27/112 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115

公开(公告)号：DE102006002735B3

公开(公告)日：2007-06-21

申请号：DE102006002735

申请日：2006-01-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SOMMER MICHAEL

IPC: H03K5/156 ,  H03K5/04

Abstract: Duty cycle correction (DCC) device has delay devices (DA, DB) which produced two groups of delayed signals from the system clock signal based on the rising and falling signal flanks respectively. The delay of the falling flank relative to the rising flank, or vice versa, is varied in steps in each of these groups until in each case the oscillation is lost. A controllable delay correction device determines a corrected clock signal from an equation and whether loss of the signal oscillation occurs first in the first or second group.

公开(公告)号：DE10260770B4

公开(公告)日：2005-10-27

申请号：DE10260770

申请日：2002-12-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SOMMER MICHAEL ,  ENDERS GERHARD

IPC: G11C11/404 ,  H01L21/334 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/108

Abstract: A memory cell comprises a trench capacitor with electrodes (9,11) and a dielectric layer (10) in the base with a vertical select transistor (TR) above this with a channel connecting electrode and a bit line (BL). The channel partly encloses the trench hole and the corresponding word line (WL) at least partly encloses the channel. Independent claims are also included for the following: (a) a memory cell arrangement as above;and (b) a production process for the above

公开(公告)号：DE10329395A1

公开(公告)日：2005-02-10

申请号：DE10329395

申请日：2003-06-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SOMMER MICHAEL

IPC: G06F12/00 ,  G06F13/16 ,  G06F13/42

Abstract: The document describes a method for transferring data between a memory device and a read/write device. In this case, a system clock is produced at a system clock rate and a data transfer clock is produced at a data transfer clock rate. In addition, control commands for controlling the data transfer are transferred in sync with the system clock, and data are transferred in line with corresponding control commands in sync with the data transfer clock. The system clock rate and the data transfer clock rate can be set as desired in this context. In particular, the data transfer clock rate is chosen to be higher than the system clock rate, which means that a higher data transfer rate than previously is possible.

公开(公告)号：DE10226660A1

公开(公告)日：2004-01-08

申请号：DE10226660

申请日：2002-06-14

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SOMMER MICHAEL ,  ENDERS GERHARD

IPC: H01L21/8242 ,  H01L27/02 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

Abstract: The memory cell according to the invention has a vertical selection transistor, via whose channel region the inner electrode of the trench capacitor can be connected to a bit line. The channel region is led to the bit line through an associated word line, which completely or partially encloses the channel region. As a result, a conductive channel can be formed within the channel region depending on the potential of the word line. Preferably, the extent of the trench hole in the word line direction is at least 1.5 times as large as in the bit line direction.

公开(公告)号：DE10208611A1

公开(公告)日：2003-05-22

申请号：DE10208611

申请日：2002-02-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SOMMER MICHAEL ,  FISCHER HELMUT ,  ZUCKERSTAETTER ANDREA

IPC: G11C11/406 ,  G11C11/408

Abstract: The digital memory or dynamic random access memory (DRAM) device has a refresh control device (13a-13f,14) that is designed to carry out a refresh cycle in the form of successive sub-cycles, whereby in at least one of these sub-cycles word lines of at least two non-adjacent segments in each segment group are sequentially activated simultaneously.

公开(公告)号：DE10051937C2

公开(公告)日：2002-11-07

申请号：DE10051937

申请日：2000-10-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HEYNE PATRICK ,  SOMMER MICHAEL ,  SCHROEGMEIER PETER ,  DIETRICH STEFAN ,  SCHOENIGER SABINE ,  WEIS CHRISTIAN ,  MARX THILO ,  MARKERT MICHAEL ,  PARTSCH TORSTEN ,  HEIN THOMAS

IPC: H03K5/00 ,  H03K5/13 ,  H03K5/133 ,  H03K5/14

Abstract: The circuit has input and output connections (1,2), first and second signal paths (3,4) with different delay times, a multiplexer (6), a drive circuit (5) with first and second programmable paths and transistors controled by complementary control signals and connected to nodes commonly connected to a multiplexer control input. Only one programmable path is programmed to be conducting and the other to be non-conducting.

公开(公告)号：DE102006040571B4

公开(公告)日：2015-10-15

申请号：DE102006040571

申请日：2006-08-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SOMMER MICHAEL ,  BOLLU MICHAEL

IPC: G11C7/22 ,  G11C7/06 ,  G11C16/26

Abstract: Vorrichtung (100) zum Auslesen einer, in einem Speicher (102) speicherbaren Speicherinformation, wobei von dem Speicher in einer Haltephase ein Leckstrom und in einer Auslesephase ein, von der Speicherinformation abhängiger Auslesestrom bereitstellbar ist, mit folgenden Merkmalen: einer durch eine einzelne Kapazität (C3) gebildeten Integrationseinrichtung (104) zum Aufintegrieren einer von dem Leckstrom hergeleiteten ersten Größe während der Haltephase und zum Bereitstellen einer, einem aufintegrierten Leckstrom entsprechenden Leckspannung sowie zum Aufintegrieren einer von dem Auslesestrom hergeleiteten zweiten Größe während der Auslesephase und zum Bereitstellen einer, einem aufintegrierten Auslesestrom entsprechenden Auslesespannung, wobei die Leckspannung einer am Ende der Haltephase an der einzelnen Kapazität (C3) abfallenden Spannung entspricht und die Auslesespannung einer am Ende der Auslesephase an der einzelnen Kapazität (C3) abfallenden Spannung entspricht; einer Rücksetzeinrichtung (212), die konfiguriert ist, um die Integrationseinrichtung zwischen der Haltephase und der Auslesephase in einen rückgesetzten Zustand zu bringen; und einer Vergleichseinrichtung (106) zum Bereitstellen eines Auslesewertes, der der Speicherinformation entspricht, abhängig von der Leckspannung und der Auslesespannung.

公开(公告)号：DE102006039877A1

公开(公告)日：2008-03-13

申请号：DE102006039877

申请日：2006-08-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SOMMER MICHAEL

IPC: H01L23/58

Abstract: A chip with a chip plane includes a functional area, a contact structure vertical with respect to the chip plane for connecting the functional area, which includes a conductive material, which has a predetermined length, and a vertical dummy-contact structure, which extends vertically into the functional area and which has an electrically conductive material and an insulation layer, the insulation layer being formed so that a current flow from an upper end of the dummy-contact structure to the functional area is prevented.