公开(公告)号：CA2713433A1

公开(公告)日：2009-08-13

申请号：CA2713433

申请日：2009-01-28

Applicant: MOTOROLA INC

Inventor： DUNN GREGORY J ,  BLAKE TERANCE B ,  FRANCOIS HOLLY L ,  LIN PETER A

IPC: H04M1/725 ,  H04M11/04 ,  H04W4/90

Abstract: A communication device contains multiple microphones that receive acoustic signals from a user and from the background. The acoustic signals from the user are enhanced using the background acoustic signals to reduce background noise. The enhanced signals are transmitted to an emergency network when an emergency call is made from the communication device. The raw signals are stored in the communication device for later retrieval or are transmitted simultaneously with the enhanced signals. The enhanced signals are transmitted using a circuit-switched voice mode while the raw signals are transmitted using a packet-switched voice mode.

公开(公告)号：AU2009210552A1

公开(公告)日：2009-08-13

申请号：AU2009210552

申请日：2009-01-28

Applicant: MOTOROLA INC

Inventor： DUNN GREGORY J ,  BLAKE TERANCE B ,  LIN PETER A ,  FRANCOIS HOLLY L

IPC: H04M1/725 ,  H04M11/04 ,  H04W4/90

Abstract: A communication device contains multiple microphones that receive acoustic signals from a user and from the background. The acoustic signals from the user are enhanced using the background acoustic signals to reduce background noise. The enhanced signals are transmitted to an emergency network when an emergency call is made from the communication device. The raw signals are stored in the communication device for later retrieval or are transmitted simultaneously with the enhanced signals. The enhanced signals are transmitted using a circuit-switched voice mode while the raw signals are transmitted using a packet-switched voice mode.

公开(公告)号：DE60036907T2

公开(公告)日：2008-08-07

申请号：DE60036907

申请日：2000-01-18

Applicant: MOTOROLA INC

Inventor： DUNN GREGORY J ,  ZHANG MIN-XIAN ,  SAVIC JOHN

IPC: H05K1/16 ,  H01C1/032 ,  H01C7/00 ,  H01C17/06 ,  H01L21/302 ,  H05K1/09 ,  H05K3/38

Abstract: Printed circuit boards with integral high and low value resistors are efficiently produced. The method of their manufacture entails applying a first layer of a low resistance material onto a dielectric substrate in a predetermined thickness and pattern. The pattern defines the electrical lengths and widths of low value resistors, as well as pairs of terminal electrode pads for the high value resistors. A second layer of a high resistance material is applied between and in contact with the top surfaces of the facing ends of each member of the terminal pad pairs. The fixed lengths, widths and thicknesses of the patterned high resistance material determine the values of the high value resistors. Conductive metal terminals are provided at the ends of the low value resistors and at the distal ends of the high value resistor pad pairs to complete the resistors.

公开(公告)号：WO2005062803A3

公开(公告)日：2006-02-16

申请号：PCT/US2004042529

申请日：2004-12-17

Applicant: MOTOROLA INC ,  DUNN GREGORY J ,  CHELINI REMY J ,  CROSWELL ROBERT T ,  DEAN TIMOTHY B ,  GAMBOA CLAUDIA V ,  SAVIC JOVICA

Inventor： DUNN GREGORY J ,  CHELINI REMY J ,  CROSWELL ROBERT T ,  DEAN TIMOTHY B ,  GAMBOA CLAUDIA V ,  SAVIC JOVICA

IPC: H05K1/16 ,  H05K3/02 ,  H05K3/42 ,  B32B9/00

CPC classification number: H05K1/162 ,  H05K3/025 ,  H05K3/429 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2201/09509 ,  H05K2201/09718

Abstract: A dielectric circuit board foil (400, 600) includes a conductive metal foil layer (210, 660), a crystallized dielectric oxide layer (405, 655) disposed adjacent a first surface of the conductive metal foil layer, a lanthanum nickelate layer (414, 664) disposed on the crystallized dielectric oxide layer, and an electrode layer (415, 665) that is substantially made of one or more base metals disposed on the lanthanum nickelate layer. The foil (400, 600) may be adhered to a printed circuit board sub-structure (700) and used to economically fabricate a plurality of embedded capacitors, including isolated capacitors of large capacitive density (> 1000 pf/mm²).

Abstract translation: 电介质电路板箔（400,600）包括导电金属箔层（210,660），邻近导电金属箔层的第一表面设置的结晶介电氧化物层（405,655），镍酸镧层（414） ，664）和基本上由设置在镍酸镧层上的一种或多种贱金属制成的电极层（415,665）。 箔（400,600）可以粘附到印刷电路板子结构（700）上，并用于经济地制造多个嵌入式电容器，包括具有大电容密度（> 1000pf / mm 2）的隔离电容器。

公开(公告)号：WO2005065274A2

公开(公告)日：2005-07-21

申请号：PCT/US2004043421

申请日：2004-12-22

Applicant: MOTOROLA INC ,  DUNN GREGORY J ,  PETSINGER JEFFREY M ,  SAVIC JOVICA

Inventor： DUNN GREGORY J ,  PETSINGER JEFFREY M ,  SAVIC JOVICA

IPC: H01Q1/38 ,  H05K1/03 ,  H05K1/16 ,  H05K3/00 ,  H05K3/06 ,  H05K3/42

CPC classification number: H05K3/0023 ,  H05K1/0366 ,  H05K1/162 ,  H05K3/064 ,  H05K3/429 ,  H05K2201/0175 ,  H05K2201/0355 ,  H05K2201/09309 ,  H05K2203/0571

Abstract: A dielectric sheet (500, 600, 1621) includes a photodielectric support layer (505, 1630) that may be glass reinforced and a dielectric laminate (510, 605). The dielectric laminate includes first and second metal foil layers (415, 660; 210, 665, 1605, 1610), and a dielectric layer (405, 655, 1620) disposed between the first and second metal foil layers. The first metal foil layer is adhered to the photodielectric support layer. In a printed circuit and patch antenna that includes the dielectric sheet, the first metal layer is patterned by removal of metal according to a circuit pattern and the photodielectric support layer is patterned by removal of dielectric material according to the circuit pattern.

Abstract translation: 电介质片（500,600,1621）包括可以玻璃增强的光电介质支撑层（505,1630）和电介质层压板（510,605）。 介电层压板包括设置在第一和第二金属箔层之间的第一和第二金属箔层（415,660; 210,665,1605,1610）以及介电层（405,655,1620）。 第一金属箔层粘附到光电介质支撑层。 在包括电介质片的印刷电路和贴片天线中，通过根据电路图案去除金属来图案化第一金属层，并且通过根据电路图案去除电介质材料来图案化光电介质支撑层。

公开(公告)号：WO2004109719A3

公开(公告)日：2005-04-21

申请号：PCT/US2004014665

申请日：2004-05-11

Applicant: MOTOROLA INC ,  DUNN GREGORY J ,  CHELINI REMY J ,  SAVIC JOVICA

Inventor： DUNN GREGORY J ,  CHELINI REMY J ,  SAVIC JOVICA

IPC: H01C7/00 ,  H01C17/065 ,  H05K1/02 ,  H05K1/09 ,  H05K1/16 ,  H05K3/12 ,  H01C1/012

CPC classification number: H01C17/065 ,  H01C7/005 ,  H05K1/0266 ,  H05K1/095 ,  H05K1/167 ,  H05K3/12 ,  H05K2201/09781 ,  H05K2203/1453

Abstract: A printed circuit polymer thick film (PTF) resistor (410, 420) includes tolerance control material (425, 426, 440) that substantially surrounds the resistor body (423) and significantly improves the linearity of resistance vs. resistor length, and significantly reduces resistor-to-resistor and board-to-board fabrication variances. In one embodiment (420), the tolerance control material is the same metallic material as the printed circuit conductors (430), and is formed in two finger patterns on each side of the resistor body, each finger pattern connected to one terminal pad (435) of the resistor. A layout cell (700) is used for fabricating the PTF resistor. A method is used for fabricating the PTF resistor.

Abstract translation: 印刷电路聚合物厚膜（PTF）电阻器（410,420）包括基本上围绕电阻体（423）的公差控制材料（425,426,440），并显着地改善了电阻与电阻器长度的线性度，并显着地降低 电阻 - 电阻和板对板制造差异。 在一个实施例（420）中，公差控制材料是与印刷电路导体（430）相同的金属材料，并且形成在电阻器主体的每一侧上的两个指形图案中，每个指形图案连接到一个端子焊盘（435 ）的电阻。 布局单元（700）用于制造PTF电阻。 一种制造PTF电阻的方法。

公开(公告)号：EP1082732A4

公开(公告)日：2006-11-22

申请号：EP00906973

申请日：2000-01-20

Applicant: MOTOROLA INC

Inventor： LEE TIEN ,  LACH LAWRENCE ,  DUNN GREGORY J

IPC: H05K1/16 ,  H01C1/01 ,  H01C7/00 ,  H01C17/06 ,  H05K3/00 ,  H05K3/46

CPC classification number: H05K1/167 ,  H05K3/0023 ,  H05K3/4644 ,  H05K2201/0187 ,  H05K2201/0317 ,  H05K2201/09509 ,  H05K2201/09672 ,  H05K2201/09845 ,  H05K2201/10045 ,  H05K2203/0361 ,  Y10T29/49082

Abstract: A thin-film metal resistor (44) suitable for a multilayer printed circuit board (12), and a method for its fabrication. The resistor (44) generally has a multilayer construction, with the individual layers (34, 38) of the resistor (44) being self-aligned with each other so that a negative mutual inductance is produced that very nearly cancels out the self-inductance of each resistor layer (34, 38). As a result, the resistor (44) has a very low net parasitic inductance. In addition, the multilayer construction of the resistor (44) reduces the area of the circuit board (12) required to accommodate the resistor (44), and as a result reduces the problem of parasitic interactions with other circuit elements on other layers of the circuit board (12).

公开(公告)号：EP1090401A4

公开(公告)日：2004-04-28

申请号：EP99964048

申请日：1999-12-02

Applicant: MOTOROLA INC

Inventor： DUNN GREGORY J ,  SAVIC JOVICA ,  BEUHLER ALLYSON ,  ZHANG MIN-XIAN ,  SIMONS EVERETT

IPC: H01G4/33 ,  H01L21/822 ,  H01L27/04 ,  H05K1/16 ,  H05K3/00 ,  H05K3/06 ,  H05K3/46 ,  H01G4/10

CPC classification number: H05K1/162 ,  H05K3/0023 ,  H05K3/064 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/0187 ,  H05K2201/09509 ,  Y10T29/435 ,  Y10T29/49155 ,  Y10T29/49165

Abstract: A method for manufacturing a microelectronic assembly to have aligned conductive regions and dielectric regions, for example, for producing integral capacitors (32), generally entails providing a substrate (10) with a first conductive layer (12), forming a dielectric layer (14) on the first conductive layer, and then forming a second conductive layer on the dielectric layer (16). A first region of the second conductive layer is then removed to expose a first region of the dielectric layer, which in turn is removed to expose a first region of the first conductive layer that is also removed. From this process, the first regions of the conductive and dielectric layers are each removed by using the overlying layer or layers as a mask, so that the remaining second regions of these layers are coextensive.

公开(公告)号：EP1053507A4

公开(公告)日：2002-07-24

申请号：EP99939643

申请日：1999-06-29

Applicant: MOTOROLA INC

Inventor： DUNN GREGORY J ,  SAVIC JOVICA ,  BEUHLER ALLYSON

IPC: G03F7/00 ,  H01C17/06 ,  H01C17/07 ,  H05K1/16 ,  H05K3/00 ,  H05K3/02 ,  H05K3/04 ,  H05K3/06 ,  H05K3/38 ,  G03C5/00

CPC classification number: H05K1/167 ,  G03F7/00 ,  H01C17/07 ,  H05K3/0023 ,  H05K3/025 ,  H05K3/048 ,  H05K3/386 ,  H05K2201/0317 ,  H05K2201/09881 ,  H05K2203/0152 ,  H05K2203/1461

Abstract: A method for manufacturing a microelectronic assembly to have a resistor (12) on a circuit board (10). The method entails applying a photosensitive dielectric to a substrate (18) to form a dielectric layer. The dielectric layer is photoimaged to polymerize a first portion (22). An electrically resistive film (14) is then applied to the dielectric layer and the dielectric layer is developed so that a portion of the resistive film remains over the second portion to form the resistor. A second dielectric layer (32) is then applied, photoimaged and developed to form openings (34). Terminations (16) can then be formed in the openings by known plating techniques. The resistive film is preferably a multilayer film that includes an electrically resistive layer, such as NiP, NiCr or other nickel alloy and a sacrificial backing such as a layer of copper.

Abstract translation: 一种用于制造微电子组件的方法有一个电阻器，并且特别是金属电阻片，具有期望的加工和尺寸特性。 该方法基因反弹需要施加光敏介电到基材以形成介电层。 该介电层被成像的照片，以在基片上的第一区域中聚合所述介电层的第一部分，留下所述电介质层的未聚合的剩余部分。 然后电阻性电影被施加到介电层和所述介电层被显影以它们的同时除去未聚合部分和的部分中的电阻膜，覆盖在该未聚合部分，如图在第二部分做了电阻膜-遗体的一部分 以形成电阻器。 另一种方法是为了应用电阻膜-前介电层暴露于辐射，然后通过电阻电影暴露介电层。 所述电阻优选膜是多层膜，没有包括电阻层，颜色：诸如NiP的，镍铬或另一种含镍基合金，和牺牲背衬：如铜层。

公开(公告)号：EP1082882A4

公开(公告)日：2005-10-12

申请号：EP00923062

申请日：2000-01-18

Applicant: MOTOROLA INC

Inventor： DUNN GREGORY J ,  ZHANG MIN-XIAN ,  SAVIC JOHN

IPC: H01C1/032 ,  H01C7/00 ,  H01C17/06 ,  H05K1/09 ,  H05K1/16 ,  H05K3/38 ,  H01L21/302

CPC classification number: H05K1/167 ,  H05K1/095 ,  H05K3/388 ,  H05K2201/0317 ,  H05K2201/0355 ,  H05K2201/0391 ,  H05K2203/0361 ,  H05K2203/0723 ,  H05K2203/1453 ,  Y10T29/49082 ,  Y10T29/49099 ,  Y10T29/4913

Abstract: Printed circuit boards (6) with integral high and low value resistors (2 and 4) are efficiently produced. The method of their manufacture entails applying a first layer of a low resistance material (8) onto a dielectric substrate (6) in a predetermined thickness and pattern. The pattern defines the electrical lengths and widths of low value resistors (2), as well as pairs of terminal electrode pads (28 and 30) for the high value resistors (4). A second layer of a high resistance material (18) is applied between and in contact with the top surfaces of the facing ends of each member of the terminal pad pairs (28 and 30). The fixed lengths, widths and thicknesses of the patterned high resistance material determine the values of the high value resistors. Conductive metal terminals are provided at the ends of the low value resistors and at the distal ends of the high value resistor pad to complete the resistors.