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公开(公告)号：DE69925720D1
公开(公告)日：2005-07-14
申请号：DE69925720
申请日：1999-03-04
Applicant: QUALCOMM INC
Inventor： SIH C , ZOU QUIZHEN , JHA K , KANG INYUP , LIN JIAN , MOTIWALA QUAEED , JOHN DEEPU , ZHANG LI , ZHANG HAITAO , LEE WAY-SHING , SAKAMAKI E , KANTAK A
Abstract: A circuit for digital signal processing calls for the use of a variable length instruction set. An exemplary DSP includes a set of three data buses (108, 110, 112) over which data may be exchanged with a register bank (120) and three data memories (102, 103, 104). A register bank (120) may be used that has registers accessible by at least two processing units (128, 130). An instruction fetch unit (156) may be included that receives instructions of variable length stored in an instruction memory (152). The instruction memory (152) may be separate from the set of three data memories (102, 103, 104).
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公开(公告)号：BR0312241A
公开(公告)日：2005-05-10
申请号：BR0312241
申请日：2003-06-28
Applicant: QUALCOMM INC
Inventor： KANG INYUP , LEVIN MARK D , NEUFELD ARTHUR J
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公开(公告)号：AT274706T
公开(公告)日：2004-09-15
申请号：AT99945487
申请日：1999-09-03
Applicant: QUALCOMM INC
Inventor： KANG INYUP , SIH GILBERT C , ZOU QIUZHEN
Abstract: The present invention is a novel and improved method and apparatus for performing position location in wireless communications system. One embodiment of the invention comprises a method for performing position location comprising the steps of receiving signal samples, generating a coarse acquisition sequence, rotating the coarse acquisition sequence yielding a rotated coarse acquisition sequence, and applying the rotated coarse acquisition sequence to the signal samples at a set of time offsets yielding correlated output data.
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公开(公告)号：AU2003251634A1
公开(公告)日：2004-01-19
申请号：AU2003251634
申请日：2003-06-28
Applicant: QUALCOMM INC
Inventor： KANG INYUP , LEVIN MARK D , NEUFELD ARTHUR J
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公开(公告)号：CA2476913A1
公开(公告)日：2003-09-04
申请号：CA2476913
申请日：2003-02-21
Applicant: QUALCOMM INC
Inventor： HUSSEINI JALAL , LI TAO , ARCEO JULIO , KANG INYUP , WEI JIAN , OISHI MOTO , RODRIGUES BRIAN , MEAGHER BRUCE , HIGGINS RICHARD
IPC: G06F11/10 , G06F3/06 , G06F7/00 , G06F12/00 , G06F12/06 , G06F12/16 , G06F13/16 , G06F13/28 , G11C7/00 , G11C7/10 , G11C14/00 , G11C16/04 , H04B7/00
Abstract: Memory architectures and techniques that support direct memory swapping between NAND Flash and SRAM with error correction coding (ECC). In a specifi c design, a memory architecture includes a first storage unit (e.g., an SRAM) operative to provide storage of data, a second storage unit (e.g., a NAND Flash) operative to provide (mass) storage of data, an EMI unit implemented within an ASIC and operative to provide control signals for the storage unit s, and a data bus coupled to both storage units and the EMI unit. The two stora ge units are implemented external to the ASIC, and each storage unit is operabl e to store data from the other storage unit via the data bus when the other storage unit is being accessed by the EMI unit. The EMI unit may include an ECC unit operative to perform block coding of data transferred to/from the second storage unit.
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Patent Agency Ranking
公开(公告)号：AU2002359551A8
公开(公告)日：2003-06-10
申请号：AU2002359551
申请日：2002-11-27
Applicant: QUALCOMM INC
Inventor： RAGHUPATHY ARUN , KANG INYUP , SEVERSON MATTHEW L
Abstract: A method and device for converting at least one narrow band RF signal, being suitable for transmission between at least one communications device suitable for receiving wide-band RF signals and at least one base station, to baseband. The method includes directly down-converting a signal spectrum including the at least one RF narrow-band signal to baseband such that the at least one narrow-band RF signal results at a low intermediate frequency (IF). And, digitally phase rotating the down-converted signal spectrum such that the at least one narrow-band RF signal is phase rotated from the low-IF to baseband.
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公开(公告)号：AU2001297548A1
公开(公告)日：2002-09-12
申请号：AU2001297548
申请日：2001-10-25
Applicant: QUALCOMM INC
Inventor： KANG INYUP
Abstract: An efficient turbo decoder. The disclosed turbo decoder includes a first mode of operation in which the turbo decoder uses a first functional loop. The first functional loop includes a memory bank, a read interleaver, a first multiplexer (MUX), a RAM file, a log-MAP decoder, a write interleaver, and a second MUX. The disclosed turbo decoder further includes a second mode of operation in which a second functional loop is used. The second functional loop includes the memory bank, the first MUX, the RAM file, the log-MAP decoder, and the second MUX. The memory bank is a dual port extrinsic memory. The disclosed turbo decoder circuit switches between the first mode and the second mode.
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公开(公告)号：CA2723046A1
公开(公告)日：2002-08-29
申请号：CA2723046
申请日：2002-02-15
Applicant: QUALCOMM INC
Inventor： LI TAO , HOLENSTEIN CHRISTIAN , KANG INYUP , WALKER BRETT C , PETERZELL PAUL E , CHALLA RAGHU , SEVERSON MATTHEW L , RAGHUPATHY ARUN , SIH GILBERT C
IPC: H03G1/00 , H04B1/16 , H03G3/00 , H03G3/20 , H03G3/30 , H04B1/30 , H04J13/00 , H04L27/22 , H04L27/38
Abstract: A direct downconversion receiver architecture having a DC loop to remove DC offset from the signal components, a digital variable gain amplifier (DVGA) to provide a range of gains, an automatic gain control (AGC) loop to provide gain control for the DVGA and RF/analog circuitry, and a serial bus interface (SBI) unit to provide controls for the RF/analog circuitry via a serial bus. The DVGA may be advantageously designed and located as described herein. The operating mode of the VGA loop may be selected based on the operating mode of the DC loop, since these two loops interact with one another. The duration of time the DC loop is operated in an acquisition mode may be selected to be inversely proportional to the DC loop bandwidth in the acquisition mode. The controls for some or all of the RF/analog circuitry may be provided via the serial bus.
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公开(公告)号：CA2434096A1
公开(公告)日：2002-08-01
申请号：CA2434096
申请日：2002-01-04
Applicant: QUALCOMM INC
Inventor： EKVETCHAVIT THUNYACHATE , KANG INYUP , VEDAM MARUTHY
Abstract: A multi-carrier filter for a wireless communications system employing a mult i- carrier signal. The multi-carrier filter includes a first mechanism for receiving the multi-carrier signal and extracting carrier signal components of the multi-carrier signal in response thereto. A second mechanism filters the carrier signal components and outputs a demodulated and filtered multi- bandwidth signal in response thereto. In the specific embodiment, the first mechanism includes a rotator. The multi-carrier signal is a 3x bandwidth mul ti- carrier signal having three carrier components. The three carrier components include a center carrier, a left carrier, and a right carrier. The center carrier, the left carrier, and the right carrier are separated by approximately 1.25 MHz. The rotator is a lookup table rotator that includes a mechanism for selectively rotating the multi-carrier-signal clockwise or counter clockwise and outputting the left carrier or the right carrier, respectively, in response thereto.
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公开(公告)号：HK1035594A1
公开(公告)日：2001-11-30
申请号：HK01106221
申请日：2001-09-04
Applicant: QUALCOMM INC
Inventor： SIH GILBERT C , ZOU QUIZHEN , JHA SANJAY K , KANG INYUP , LIN JIAN , MOTIWALA QUAEED , JOHN DEEPU , ZHANG LI , ZHANG HAITAO , LEE WAY-SHING , SAKAMAKI CHARLES E , KANTAK PRASHANT A
Abstract: A circuit for digital signal processing calls for the use of a variable length instruction set. An exemplary DSP includes a set of three data buses (108, 110, 112) over which data may be exchanged with a register bank (120) and three data memories (102, 103, 104). A register bank (120) may be used that has registers accessible by at least two processing units (128, 130). An instruction fetch unit (156) may be included that receives instructions of variable length stored in an instruction memory (152). The instruction memory (152) may be separate from the set of three data memories (102, 103, 104).
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