公开(公告)号：FR2865850B1

公开(公告)日：2006-08-04

申请号：FR0401018

申请日：2004-02-03

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  CHANEMOUGAME DANIEL ,  MONFRAY STEPHANE

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/786

公开(公告)号：FR2844396A1

公开(公告)日：2004-03-12

申请号：FR0302772

申请日：2003-03-06

Applicant: ST MICROELECTRONICS SA ,  FRANCE TELECOM

Inventor： BUSTOS JESSY ,  CORONEL PHILIPPE ,  REGNIER CHRISTOPHE ,  WACQUANT FRANCOIS ,  TAVEL BRICE ,  SKOTNICKI THOMAS

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

Abstract: The production of an electronic component consists of: (a) covering the surface (S) of a substrate (100) with a portion (P) delimiting with the substrate a volume (V) filled at least partially with a temporary material; (b) evacuating the temporary material from the volume by a shaft (C) extending between the volume and an access surface; (c) introducing an electrical conducting filling material (7) into the volume from some precursors fed via the shaft. Independent claims are also included for: (1) a field effect transistor with a gate produced by this method; (2) an electronic device incorporating such a transistor.

公开(公告)号：FR2818012B1

公开(公告)日：2003-02-21

申请号：FR0016174

申请日：2000-12-12

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  MONFRAY STEPHANE ,  HAOND MICHEL

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/80 ,  H01L27/105

Abstract: An electronic device, such as an opto-electronic device and an integrated semiconductor memory device, includes at least one integrated memory point structure including a quantum well semiconductor area buried in the substrate of the structure and disposed under the insulated gate of a transistor. A biasing voltage source is adapted to bias the structure to enable charging or discharging of charges in the quantum well or outside the quantum well.

公开(公告)号：FR2823010A1

公开(公告)日：2002-10-04

申请号：FR0104437

申请日：2001-04-02

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  JOSSE EMMANUEL

IPC: H01L21/336 ,  H01L29/165 ,  H01L29/78

Abstract: Production of a vertical transistor having an insulated gate with four-channel conduction comprises forming a vertical semiconductor column on a semiconductor substrate, and forming a dielectrically insulated semiconductor gate on the sides of the column and on the upper surface of the substrate. Formation of the column (PIL) comprises forming a first semiconductor column on the substrate, and forming a cavity in the primary column. Formation of the insulated gate comprises coating the internal walls of the cavity with a dielectric insulating material and filling the insulated cavity with gate material (14), so as to form, between the part of the insulated gate located in the cavity and the part of the insulated grid located on the sides of the column, two semiconductor connection regions (PL1, PL2) extending between the source and the drain of the transistor. An Independent claim is given for an integrated circuit comprising the vertical transistor.

公开(公告)号：FR2806833B1

公开(公告)日：2002-06-14

申请号：FR0003844

申请日：2000-03-27

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  JURCZAK MALGORZATA ,  HAOND MICHEL

IPC: H01L21/336 ,  H01L29/786 ,  H01L29/78

Abstract: A method for making a MOS transistor includes forming a first gate within a silicon-on-insulator substrate, forming a semiconductor channel region transversely surmounting the first gate, and forming semiconductor drain and source regions on each side of the channel region. The semiconductor channel region and drain and source regions may be produced by epitaxy on an upper surface of the first gate. The channel region may be isolated from the upper surface of the first gate by forming a tunnel under the channel region and at least partially filling the tunnel with a first dielectric. The second gate is formed on the channel region and transverse to the channel region. The second gate may be separated from an upper surface of the channel region by a second dielectric.

公开(公告)号：FR2801970A1

公开(公告)日：2001-06-08

申请号：FR9915410

申请日：1999-12-07

Applicant: ST MICROELECTRONICS SA

Inventor： JAOUEN HERVE ,  SKOTNICKI THOMAS ,  JURCZAK MALGORZATA

IPC: G01D5/242 ,  G01L9/00 ,  G10K9/13 ,  G01D5/241 ,  H01L43/12

Abstract: The invention concerns a magnetic sensor comprising a thin deformable membrane (3) made of conductive material forming a first armature of a capacitor and traversed by an electric current, a second armature of a capacitor consisting of a doped zone of a semiconductor substrate (1), and a gaseous dielectric layer (6) separating the two armatures. The membrane is deformed under the effect of the Lorentz force generated by a magnetic field located in the plane of the membrane and perpendicular to the current lines. The invention also concerns a method for making said magnetic sensor and a device for measuring magnetic field.

公开(公告)号：FR2790598B1

公开(公告)日：2001-06-01

申请号：FR9902513

申请日：1999-03-01

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  ALIEU JEROME

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/336 ,  H01L21/762 ,  H01L29/10 ,  H01L29/772 ,  H01L29/161

Abstract: A transistor has an indium-doped Si-Ge buried layer located in a region of a silicon channel. An indium-implanted transistor has a silicon channel region in which a buried layer of an indium-implanted alloy Si1-xGex, where 10 ≤ x ≤ 4 x 10 , preferably 10 ≤ x ≤ 10 . The amount of implanted indium is 1 x 10 -4 x 10 atoms/cm , preferably 5 x 10 -5 x 10 atoms/cm . The implanted indium has an implantation profile that is electrically active, retrograde and stable, and approaches the profile of indium chemical retrograde implantation. Independent claims are given for methods of production of the transistor. One method comprises: (a) producing, on at least one zone in the surface of a silicon substrate, the zone being intended to form a region of a transistor channel, a multilayered composite film comprising, successively from the initial surface of the substrate, at least one Si1-xGex alloy layer, as above, and an external silicon layer of at least 5 nm thickness; (b) implanting indium into the Si1-xGex alloy layer; and (c) completing the fabrication of a transistor in order to obtain a transistor whose channel region comprises a buried layer of indium-implanted Si1-xGex.

公开(公告)号：FR3018389B1

公开(公告)日：2017-09-01

申请号：FR1451833

申请日：2014-03-06

Applicant: ST MICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： TRIOUX EMILIE ,  ANCEY PASCAL ,  MONFRAY STEPHANE ,  SKOTNICKI THOMAS ,  BASROUR SKANDAR ,  MURALT PAUL

IPC: H01L21/203 ,  H01L41/08 ,  H01L41/18 ,  H01L41/27

公开(公告)号：FR2860099B1

公开(公告)日：2006-01-06

申请号：FR0310984

申请日：2003-09-18

Applicant: ST MICROELECTRONICS SA

Inventor： SKOTNICKI THOMAS ,  CORONEL PHILIPPE ,  HARTMANN JOEL

IPC: H01L21/336 ,  H01L27/11 ,  H01L29/423 ,  H01L29/786

公开(公告)号：FR2853454B1

公开(公告)日：2005-07-15

申请号：FR0304143

申请日：2003-04-03

Applicant: ST MICROELECTRONICS SA

Inventor： CORONEL PHILIPPE ,  MORAND YVES ,  SKOTNICKI THOMAS ,  CERUTTI ROBIN

IPC: H01L21/336 ,  H01L29/423 ,  H01L29/786 ,  H01L29/78

Abstract: A MOS transistor formed in a silicon substrate (101) comprises: (a) an active zone (100) surrounded by an insulating partition (102); (b) a first conducting strip (103) covering a central strip of the active zone; (c) one or more second conducting strips (105, 106, 107) placed in the active zone plumb with the first strip; (d) some conducting regions (108, 109) placed in two cavities in the insulating partition and joined to the ends of the first and second strips; (e) the surfaces of the silicon opposite the strips and conducting regions are covered with an insulator (130) constituting an oxide grid. An independent claim is also included for the production of this MOS transistor.