公开(公告)号：EP0863392A1

公开(公告)日：1998-09-09

申请号：EP97830093.7

申请日：1997-03-04

Applicant: STMicroelectronics S.r.l.

Inventor： Vigna, Benedetto ,  Ferrari, Paolo ,  Montanini, Pietro ,  Ferrera, Marco

IPC: G01L9/00

CPC classification number: G01L9/0054 ,  G01L9/0055

Abstract: The method described provides for the formation of a region of silicon dioxide on a substrate (11) of monocrystalline silicon, the epitaxial growth of a silicon layer, the opening of holes (14') in the silicon layer above the silicon dioxide region, and the removal of the silicon dioxide which constitutes the region by means of chemical attack through the holes (14') until a silicon diaphragm (12'), attached to the substrate (11) along the edges and separated therefrom by a space (15), is produced. In order to form an absolute pressure microsensor, the space has to be sealed. To do this, the method provides for the holes (14') to have diameters smaller than the thickness of the diaphragm (12') and to be closed by the formation of a silicon dioxide layer (16) by vapour-phase deposition at atmospheric pressure.

Abstract translation: 所述方法提供了在单晶硅的衬底（11）上形成二氧化硅区域，硅层的外延生长，在二氧化硅区域上方的硅层中的孔（14'）的开口，以及 通过所述孔（14'）的化学侵蚀去除构成所述区域的二氧化硅，直到沿着所述边缘附着到所述基板（11）并通过空间（15）分离的硅隔膜（12'）， ，被生产。 为了形成绝对压力微传感器，必须密封空间。 为此，该方法提供孔（14'）具有小于隔膜（12'）的厚度的直径并且通过在大气中气相沉积形成二氧化硅层（16）来封闭 压力。

公开(公告)号：EP2264753A3

公开(公告)日：2011-04-20

申请号：EP10183038.8

申请日：2006-06-27

Applicant: STMicroelectronics S.r.l.

Inventor： Montanini, Pietro ,  Ammendola, Giuseppe ,  Depetro, Riccardo ,  Mottura, Marta

IPC: H01L21/76 ,  H01L21/84 ,  H01L27/12 ,  H01L21/762

CPC classification number: H01L21/84 ,  H01L21/26586 ,  H01L21/3226 ,  H01L21/76264 ,  H01L27/1207

Abstract: A method is proposed for manufacturing an integrated electronic device (500). The method includes the steps of providing an SOI substrate (505) including a semiconductor substrate (510), an insulating layer (515) on the semiconductor substrate, and a semiconductor starting layer (512) on the insulating layer, the substrate and the starting layer being of a first type of conductivity, performing an epitaxial growing process, the epitaxial growing process being applied to the starting layer to obtain a thicker semiconductor active layer (542) of the first type of conductivity embedding the starting layer on the insulating layer, forming at least one insulating trench (558) extending from an exposed surface of the active layer to the insulating layer, the at least one insulating trench partitioning the active layer into insulated regions (560) and at least one further insulated region (561), and integrating components (580) of the device in the insulated regions, the components being insulated from the substrate by the insulating layer; in the solution according to an embodiment of the invention, the method further includes, before the step of performing an epitaxial growing process, forming at least one contact trench (520) extending from an exposed surface of the starting layer to the substrate in correspondence to each further insulated region, each contact trench clearing a corresponding portion (530b,530s) of the starting layer, of the insulating layer and of the substrate, implanting dopants of a second type of conductivity different from the first type into at least part of the cleared portions, wherein the epitaxial growing is further applied to the cleared portions thereby at least partially filling each contact trench with semiconductor material, the dopants diffusing during the epitaxial growing to form an insulating region (545) of the second type of conductivity enclosing the at least one contact trench of each further insulated region, and integrating further components (580) of the device in each further insulated region, the further components being insulated from the substrate by a junction formed by the corresponding insulating region with the active layer and/or the substrate when reverse-biased.

公开(公告)号：EP1786031A1

公开(公告)日：2007-05-16

申请号：EP05110577.3

申请日：2005-11-10

Applicant: STMicroelectronics S.r.l.

Inventor： Annese, Marco ,  Toia, Fabrizio Fausto ,  Montanini, Pietro

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L21/28167 ,  H01L29/42368 ,  H01L29/66621 ,  H01L29/7834

Abstract: A vertical-gate MOS transistor ( 100 ) is proposed. The vertical-gate MOS transistor is integrated in a semiconductor chip ( 120 ) of a first conductivity type having a main surface, and includes an insulated trench gate ( 110 ) extending into the semiconductor chip from the main surface to a gate depth ( d1 ), said trench gate including a control gate ( G ) and an insulation layer ( 180 ) for insulating the control gate from the semiconductor chip, a source region and a drain region of a second conductivity type formed in the semiconductor chip, at least one of the source region and drain region being adjacent to the insulation layer and extending into the semiconductor chip from the main surface to a region depth ( d2 ) lower than the gate depth, wherein the insulation layer includes an external portion ( 180a ), extending into the semiconductor chip from the main surface to a protection depth ( d4 ) lower than the gate depth, and a remaining internal portion ( 180b ), the external portion having an external thickness ( d5 ) and the internal portion having an internal thickness ( d6 ) lower than the external thickness.

Abstract translation: 提出了垂直栅极MOS晶体管（100）。 垂直栅极MOS晶体管集成在具有主表面的第一导电类型的半导体芯片（120）中，并且包括从主表面延伸到栅极深度（d1）的半导体芯片中的绝缘沟槽栅极（110） 所述沟槽栅极包括控制栅极（G）和用于使控制栅极与半导体芯片绝缘的绝缘层（180），形成在半导体芯片中的第二导电类型的源极区域和漏极区域，至少一个 所述源极区域和漏极区域与所述绝缘层相邻并且从所述主表面延伸到所述半导体芯片中至低于所述栅极深度的区域深度（d2），其中所述绝缘层包括外部部分（180a），所述外部部分延伸到 半导体芯片从主表面到比栅极深度低的保护深度（d4），以及剩余内部部分（180b），外部部分具有外部厚度（d5）和i 内部部分具有比外部厚度低的内部厚度（d6）。

公开(公告)号：EP1742270A1

公开(公告)日：2007-01-10

申请号：EP05106115.8

申请日：2005-07-06

Applicant: STMicroelectronics S.r.l.

Inventor： Montanini, Pietro ,  Annese, Marco ,  Zullino, Lucia

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L21/265 ,  H01L21/336

CPC classification number: H01L29/66621 ,  H01L21/2652 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/6659 ,  H01L29/7834

Abstract: An insulated-gate transistor (100) includes a semiconductor layer (120) of a first conductivity type, an insulated gate comprising a trench gate (110) extending into the semiconductor layer, a source and a drain regions of a second conductivity type formed in the semiconductor layer at respective sides of the trench gate, wherein each one of the source and drain regions includes a first doped region (130,140), having a first dopant concentration, formed in the semiconductor layer adjacent to the trench gate, said first dopant concentration being such that a breakdown voltage of the junction formed by the first doped region and the semiconductor layer is higher than a predetermined breakdown voltage, and a second doped region (150,160), having a second dopant concentration higher than the first dopant concentration, said second doped region being formed in the first doped region and being spaced apart from the trench gate, the second dopant concentration being adapted to form a non-rectifying contact for electrically contacting the first doped region.

Abstract translation: 绝缘栅晶体管（100）包括第一导电类型的半导体层（120），包括延伸到半导体层中的沟槽栅极（110）的绝缘栅极，形成在第二导电类型中的第二导电类型的源极区域和漏极区域 所述沟槽栅极的相应侧的所述半导体层，其中所述源极和漏极区域中的每一个包括形成在与所述沟槽栅极相邻的所述半导体层中的第一掺杂剂浓度的第一掺杂区域，所述第一掺杂浓度 使得由第一掺杂区域和半导体层形成的结的击穿电压高于预定的击穿电压;以及具有高于第一掺杂剂浓度的第二掺杂浓度的第二掺杂区域（150,160），所述第二掺杂区域 掺杂区域形成在第一掺杂区域中并且与沟槽栅极间隔开，第二掺杂剂浓度适于形成非直角 用于电接触第一掺杂区域。

公开(公告)号：EP1659640A1

公开(公告)日：2006-05-24

申请号：EP04425867.1

申请日：2004-11-19

Applicant: STMicroelectronics S.r.l.

Inventor： Montanini, Pietro ,  Riboli, Paolo ,  Zanotti, Luca ,  Palmieri, Michele ,  Mottura, Marta

IPC: H01L31/18 ,  H01L31/068 ,  H01L21/762

CPC classification number: H01L31/1804 ,  H01L31/068 ,  Y02E10/547 ,  Y02P70/521

Abstract: A method of fabricating a wafer-size photovoltaic cell module capable of drastically reducing the overall costs of photovoltaic cells of enhanced efficiency realized on a monocrystalline silicon substrate comprises the steps of:

defining an integrated cellular structure, of a light converting monolateral or bilateral junction diode in the epitaxially grown detachable layer, including a first deposited metal current collecting terminal of the diode;
laminating onto the surface the processed epitaxially grown detachable layer a film of an optical grade plastic material resistant to hydrofluoric acid solutions;
immersing the wafer in a hydrofluoric acid solution causing detachment of the processed epitaxially grown silicon layer laminated with the film of optical grade plastic material;
polishing the surface of separation of the detached processed epitaxially grown layer and forming a second metal current collecting terminal of the diode by masked deposition of a metal at a relatively low temperature tolerable by the film of optical grade plastic material.

Abstract translation: 制造能够大幅度地减少的实现上的单晶硅衬底增强效率的光伏电池的总成本的晶片尺寸太阳能电池组件的方法，包括以下步骤：光的集成蜂窝结构的 - 定义，转换单边或双边结二极管 在外延生长层可拆卸的，包括第一熔敷金属集流二极管的端子; 到表面上的处理外延生长可分离层层压的光学级塑料材料，以氢氟酸溶液腐蚀的膜; 浸渍在曹景伟层叠有光学级塑料材料制成的膜经处理的外延生长的硅层的剥离氢氟酸溶液的晶片; 抛光处理分离外延生长层的分离表面以及形成第二金属电流在相对低的温度下的光学级塑料材料制成的膜可容忍收集二极管通过金属的掩蔽沉积的终端。

公开(公告)号：EP0948034B1

公开(公告)日：2005-01-05

申请号：EP98830206.3

申请日：1998-04-03

Applicant: STMicroelectronics S.r.l.

Inventor： Montanini, Pietro ,  Villa, Flavio ,  Barlocchi, Gabriele

IPC: H01L21/3065 ,  H01L21/762

CPC classification number: H01L21/3065 ,  H01L21/76248 ,  H01L21/76294

公开(公告)号：EP0863392B1

公开(公告)日：2000-08-09

申请号：EP97830093.7

申请日：1997-03-04

Applicant: STMicroelectronics S.r.l.

Inventor： Vigna, Benedetto ,  Ferrari, Paolo ,  Montanini, Pietro ,  Ferrera, Marco

IPC: G01L9/00

CPC classification number: G01L9/0054 ,  G01L9/0055

公开(公告)号：EP0948034A1

公开(公告)日：1999-10-06

申请号：EP98830206.3

申请日：1998-04-03

Applicant: STMicroelectronics S.r.l.

Inventor： Montanini, Pietro ,  Villa, Flavio ,  Barlocchi, Gabriele

IPC: H01L21/3065 ,  H01L21/762

CPC classification number: H01L21/3065 ,  H01L21/76248 ,  H01L21/76294

Abstract: The method includes the steps of: on a wafer (1) of monocrystalline semiconductor material, forming a hard mask (9') of an oxidation-resistant material, defining first protective regions (7) covering first portions (21) of the wafer (1); and forming first trenches (10'') in the wafer (1). The first trenches are formed by two etching steps: firstly, the portions (8'') of the wafer (1) not covered by the hard mask (9') are isotropically etched, such as to remove the semiconductor material not only from the portions without a mask, but also partially below the first protective regions (7); then anisotropic etching is carried out. After forming second protective regions (30) incorporating the first protective regions (7), final trenches (16) are formed, and the semiconductor material of wafer (1) is oxidised, except for the portions (21) which are covered by the second protective regions (30), in order to form a continuous oxide region (22); after removal of the second protective regions (30), a monocrystalline layer (23) is grown epitaxially from the non-oxidised portions (21).

Abstract translation: 该方法包括以下步骤：在单晶半导体材料的晶片（1）上形成抗氧化材料的硬掩模（9'），限定覆盖晶片的第一部分（21）的第一保护区域（7） 1）; 以及在所述晶片（1）中形成第一沟槽（10“）。 第一沟槽由两个蚀刻步骤形成：首先，未被硬掩模（9'）覆盖的晶片（1）的部分（8“）被各向同性地蚀刻，例如不仅从 没有掩模的部分，但也部分地在第一保护区域（7）下面; 然后进行各向异性蚀刻。 在形成并入有第一保护区域（7）的第二保护区域（30）之后，形成最终沟槽（16），并且晶片（1）的半导体材料被氧化，除了由第二保护区域 保护区域（30），以形成连续氧化物区域（22）; 在除去第二保护区域（30）之后，从非氧化部分（21）外延生长单晶层（23）。

公开(公告)号：EP2264752A3

公开(公告)日：2011-04-20

申请号：EP10182985.1

申请日：2006-06-27

Applicant: STMicroelectronics S.r.l.

Inventor： Montanini, Pietro ,  Ammendola, Giuseppe ,  Depetro, Riccardo ,  Mottura, Marta

IPC: H01L21/322 ,  H01L21/84 ,  H01L21/762

CPC classification number: H01L21/84 ,  H01L21/26586 ,  H01L21/3226 ,  H01L21/76264 ,  H01L27/1207

Abstract: A method is proposed for manufacturing an integrated electronic device (400) of the SOI type. The method includes the steps of providing an SOI substrate (105) including a semiconductor substrate (110), an insulating layer (115) on the semiconductor substrate, and a semiconductor starting layer (112) on the insulating layer, performing an epitaxial growing process, the epitaxial growing process being applied to the starting layer to obtain a thicker semiconductor active layer (142) embedding the starting layer on the insulating layer, forming at least one insulating trench (405) extending from an exposed surface of the active layer to the insulating layer, the at least one insulating trench partitioning the active layer into insulated regions (415) and at least one further insulated region (425), and integrating components (420) of the device in the insulated regions; in the solution according to an embodiment of the invention, the method further includes, before the step of performing an epitaxial growing process, forming at least one contact trench (120) extending from an exposed surface of the starting layer to the substrate in correspondence to each further insulated region, wherein each contact trench clears a corresponding portion (130b,130s) of the starting layer, of the insulating layer and of the substrate, the epitaxial growing being further applied to the cleared portions thereby at least partially filling each contact trench with semiconductor material gettering impurities of the active layer, the gettered impurities in the at least one further insulated region being segregated from the insulated regions.

公开(公告)号：EP1873822A1

公开(公告)日：2008-01-02

申请号：EP06116133.7

申请日：2006-06-27

Applicant: STMicroelectronics S.r.l.

Inventor： Montanini, Pietro ,  Toia, Fabrizio Fausto Renzo ,  Mottura, Marta

IPC: H01L21/762

CPC classification number: H01L21/84 ,  H01L21/743 ,  H01L21/76283 ,  H01L21/76898 ,  H01L27/1203 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An electronic device (100, 100', 760) is proposed. The device is integrated in a chip (705) including at least one stacked layer having a front surface (140, 708) and a rear surface (743) opposite the front surface, the device including: an insulating trench (120,120', 718) insulating an active region (125, 747) of the chip, the insulating trench having a section across each plane parallel to the front surface extending along a longitudinal line (207, 207'), and a front-rear contact (430,436, 440) electrically contacting the front surface to the rear surface in the active region, wherein the section of the insulating trench has a non-uniform width along the longitudinal line, and/or the device further includes at least one further insulating trench (170) within the active region.

Abstract translation: 一种电子装置（100，100”，760）的提议。 该装置被集成在一个芯片（705）包括具有前表面（140，708）的至少一个堆叠层和后表面（743）与前表面相对，该装置包括：一个绝缘槽（120,120”，718） 绝缘的芯片，具有横跨每一个部分中的绝缘沟槽，并平行于前表面沿纵向线（207“207）（430.436，440）延伸的前，后接触面的有源区（125，747） 电接触的前表面到后表面在有源区，worin绝缘沟槽的部分具有沿着所述纵向线的非均匀的宽度，和/或该设备进一步包括至少一个另外的内绝缘沟槽（170） 有源区。