公开(公告)号：EP3800660A1

公开(公告)日：2021-04-07

申请号：EP20198891.2

申请日：2020-09-29

Applicant: STMicroelectronics S.r.l.

Inventor： RASCUNA, Simone ,  CHIBBARO, Claudio ,  GUARNERA, Alfio ,  SAGGIO, Mario Giuseppe ,  LIZIO, Francesco

IPC: H01L23/31

Abstract: An electronic power device (25) is provided with: a substrate (2) of silicon carbide (SiC), having a front surface (2a) and a rear surface (2b), which lie in a horizontal plane (xy) and are opposite to one another along a vertical axis (z), the substrate including an active area (A'), provided in which are a number of doped regions (4), and an edge area (A"), which is not active, distinct from and surrounding the active area (A'); a dielectric region (8a) arranged above the front surface (2a), at least at the edge area (A"); and a passivation layer (20) arranged above the front surface (2a) of the substrate (2), in contact with the dielectric region (8a) in the edge area (A"). The passivation layer (20) comprises at least one anchorage region (22) that extends throughout the thickness of the dielectric region (8a) at the edge area (A"), such as to define a mechanical anchorage for the passivation layer (20).

公开(公告)号：EP4333027A1

公开(公告)日：2024-03-06

申请号：EP23190768.4

申请日：2023-08-10

Applicant: STMicroelectronics S.r.l.

Inventor： SAGGIO, Mario Giuseppe ,  CAMALLERI, Cateno Marco ,  BELLOCCHI, Gabriele ,  RASCUNA', Simone

IPC: H01L21/336 ,  H01L29/45 ,  H01L29/78 ,  H01L29/12

Abstract: Method of manufacturing an electronic device (20), comprising forming an ohmic contact (59; 61) at an implanted region (26; 55) of a semiconductor body (48). Forming the ohmic contact provides for performing a high-temperature thermal process for allowing a reaction between a metal material and the material of the semiconductor body, for forming a silicide of the metal material. The step of forming the ohmic contact is performed prior to a step of forming one or more electrical structures (52, 56) which include materials that may be damaged by the high temperature of the thermal process of forming the silicide.

公开(公告)号：EP4254511A1

公开(公告)日：2023-10-04

申请号：EP23161989.1

申请日：2023-03-15

Applicant: STMicroelectronics S.r.l.

Inventor： CASCINO, Salvatore ,  GUARNERA, Alfio ,  SAGGIO, Mario Giuseppe

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423

Abstract: Electronic device comprising: a semiconductor body (8, 10) having a first electrical conductivity (N) and provided with a front side (1a); an active area (4) of the semiconductor body, accommodating the source (12) and gate (14) regions of the electronic device and configured to accommodate, in use, a conductive channel of the electronic device; and an edge region (6) of the electronic device, surrounding the active area (4) and accommodating at least in part: i) an edge termination region (20), having a second electrical conductivity (P) opposite to the first electrical conductivity (N), extending into the semiconductor body at the front side (1a); and ii) a gate connection terminal (24) of conductive material, electrically coupled to the gate region (14), extending on the front side (1a) partially superimposed on the edge termination region (20) and capacitively coupled with a portion of the semiconductor body adjacent and external to the edge termination region (20) .

公开(公告)号：EP4036957A1

公开(公告)日：2022-08-03

申请号：EP22153333.4

申请日：2022-01-25

Applicant: STMicroelectronics S.r.l.

Inventor： SAGGIO, Mario Giuseppe ,  FRAZZETTO, Alessia Maria ,  ZANETTI, Edoardo ,  GUARNERA, Alfio

IPC: H01L21/336 ,  H01L29/16 ,  H01L21/04 ,  H01L29/78 ,  H01L29/08 ,  H01L29/417

Abstract: The vertical conduction MOSFET device (100) is formed by a body (105) of silicon carbide, which has a first conductivity type and a face (105A); by a metallization region (140), which extends on the face of the body; by a body region (115) of a second conductivity type different from the first conductivity type, which extends in the body, from the face of the body, along a first direction (Y) parallel to the face and along a second direction (Z) transverse to the face; and by a source region (120) of the first conductivity type, which extends towards the inside of the body region, from the face of the body. The source region has a first portion (120A) and a second portion (120B), wherein the first portion has a first doping level and extends in direct electrical contact with the metallization region, wherein the second portion has a second doping level and extends in direct electrical contact with the first portion of the source region, and wherein the second doping level is lower than the first doping level.

公开(公告)号：EP4020595A1

公开(公告)日：2022-06-29

申请号：EP21217608.5

申请日：2021-12-23

Applicant: STMicroelectronics S.r.l.

Inventor： FIORENZA, Patrick ,  ROCCAFORTE, Fabrizio ,  ZANETTI, Edoardo ,  SAGGIO, Mario Giuseppe

IPC: H01L29/78 ,  H01L21/336 ,  H01L29/12 ,  H01L29/08

Abstract: A MOSFET transistor device has: a functional layer (24) of silicon carbide, having a first conductivity type; gate structures (30) formed on a top surface (24a) of the functional layer and each comprising a dielectric region (31) and an electrode region (32); body wells (26) having a second conductivity type, formed within the functional layer, separated from one another by surface-separation regions (29); source regions (27) having the first conductivity type, formed within the body wells, laterally and partially underneath respective gate structures. Modified-doping regions (40) are arranged in the surface-separation regions centrally thereto, underneath respective gate structures, in particular underneath the corresponding dielectric regions, and have a modified concentration of dopant as compared to the concentration of the functional layer.

公开(公告)号：EP3742496A1

公开(公告)日：2020-11-25

申请号：EP20176149.1

申请日：2020-05-22

Applicant: STMicroelectronics S.r.l.

Inventor： FIORENZA, Patrick ,  ROCCAFORTE, Fabrizio ,  SAGGIO, Mario Giuseppe

IPC: H01L29/51 ,  H01L29/78 ,  H01L29/872 ,  H01L21/336 ,  H01L29/12

Abstract: An electronic device comprising: a semiconductor body (48; 68) of silicon carbide, SiC, having a first (48a; 68a) and a second face (48b; 68b), opposite to one another along a first direction (Z), which presents positive-charge carriers at said first face that form a positive interface charge; a first conduction terminal (S; 74), which extends at the first face of the semiconductor body; a second conduction terminal (D; 72), which extends on the second face of the semiconductor body; a channel region in the semiconductor body, configured to house, in use, a flow of electrons between the first conduction terminal and the second conduction terminal; and a trapping layer (52; 80), of insulating material, which extends in electrical contact with the semiconductor body at said channel region and is designed so as to present electron-trapping states that generate a negative charge such as to balance, at least in part, said positive interface charge.

公开(公告)号：EP3712962A1

公开(公告)日：2020-09-23

申请号：EP20164124.8

申请日：2020-03-19

Applicant: STMicroelectronics S.r.l.

Inventor： RASCUNA, Simone ,  SAGGIO, Mario Giuseppe

IPC: H01L29/872 ,  H01L29/06 ,  H01L29/16 ,  H01L21/329 ,  H01L29/20

Abstract: A merged-PN-Schottky, MPS, diode (30), comprising: an N substrate (3); a N- drift layer (2); a P-doped region (19') in the drift layer (2); an ohmic contact (19") on the P-doped region (19'); a plurality of cells (33) within the P-doped region and being portions of the drift layer where the P-doped region (19') is absent; an anode metallization (8) on the ohmic contact (19") and on said cells (33), to form junction-barrier contacts and Schottky contacts respectively. The P-doped region (19') has a grid-shaped layout separating from one another each cell (33) and defining, together with the cells (33), an active area (14) of the MPS diode (30); each cell (33) has a same geometry among quadrangular, quadrangular with rounded corners and circular; and the ohmic contact (19") extends at the doped region (19') with continuity along the grid-shaped layout.

公开(公告)号：EP4307384A2

公开(公告)日：2024-01-17

申请号：EP23181494.8

申请日：2023-06-26

Applicant: STMicroelectronics S.r.l.

Inventor： CAMALLERI, Cateno Marco ,  SAGGIO, Mario Giuseppe ,  GUARNERA, Alfio

IPC: H01L29/06 ,  H01L29/49 ,  H01L29/78 ,  H01L29/423

Abstract: A power MOSFET device (1) comprises a semiconductor body (3) having a first main surface (3a). The semiconductor body (3) includes an active area (7) facing the first main surface (3a). The power MOSFET device (1) comprises an isolated-gate structure (15), which extends over the active area (7) and includes a gate-oxide layer (12), which is made of insulating material and extends over the first main surface (3a), and a gate region (24) buried in the gate-oxide layer (12) so as to be electrically insulated from the semiconductor body (3). The gate region (24) comprises a gate layer (14) of polysilicon and at least one first silicide region (25a) and one second silicide region (25b), which extend in the gate layer (14) so as to face a top surface (14a) of the gate layer (14) and to be arranged alongside one another and spaced apart from one another in a first plane (XY).

公开(公告)号：EP4156241A1

公开(公告)日：2023-03-29

申请号：EP22195558.6

申请日：2022-09-14

Applicant: STMicroelectronics S.r.l.

Inventor： SAGGIO, Mario Giuseppe ,  GUARNERA, Alfio

IPC: H01L21/82 ,  H01L27/06 ,  H01L29/16 ,  H01L29/78

Abstract: A silicon carbide power device (100) has: a die (2) having a functional layer (4) of silicon carbide and an edge area (2a) and an active area (2b), surrounded by the edge area (2a); gate structures (3') formed on a top surface (4a) of the functional layer (4) in the active area (2b); and a gate contact pad (18) for biasing the gate structures (3'). The device also has an integrated resistor (30) having a doped region (32), of a first conductivity type (N + ), arranged at the front surface (4a) of the functional layer (4) in the edge area (2a); wherein the integrated resistor (30) defines an insulated resistance in the functional layer (4), interposed between the gate structures (3') and the gate contact pad (18).

公开(公告)号：EP4036986A1

公开(公告)日：2022-08-03

申请号：EP22154043.8

申请日：2022-01-28

Applicant: STMicroelectronics S.r.l.

Inventor： SAGGIO, Mario Giuseppe ,  ZANETTI, Edoardo ,  FRAZZETTO, Alessia Maria ,  GUARNERA, Alfio ,  CAMALLERI, Cateno Marco ,  GRIMALDI, Antonio Giuseppe

IPC: H01L29/10 ,  H01L29/66 ,  H01L29/16 ,  H01L29/78 ,  H01L21/04 ,  H01L29/417

Abstract: The vertical conduction MOSFET device (100)is formed by a body (105) of silicon carbide, which has a first type of conductivity and a face (105A), and by a superficial body region (115) of a second type of conductivity, which has a first doping level, extends into the body, from the face of the body, to a first depth (d sb ) along a first direction, and has a first width (W sb ) along a second direction transversal to the first direction. The MOSFET device is also formed by a source region (120) and by a deep body region (110). The source region is of the first type of conductivity, extends to the inside of the superficial body region, from the face of the body, to a second depth (d b ), along the first direction, and has a second width (W s ) along the second direction, wherein the second depth is smaller than the first depth and the second width is smaller than the first width. The deep body region is of the second type of conductivity, has a second doping level and extends into the body, at a distance from the face of the body and in direct electrical contact with the superficial body region, wherein the second doping level is higher than the first doping level.