公开(公告)号：KR1020150079325A

公开(公告)日：2015-07-08

申请号：KR1020130169491

申请日：2013-12-31

Applicant: 노틸러스효성 주식회사

Inventor： 박태원

IPC: H03M1/08

CPC classification number: H03M1/08 ,  H03M1/0609 ,  H03M1/1023 ,  H03M2201/11 ,  H03M2201/192 ,  H03M2201/6327 ,  H03M2201/64

Abstract: 본발명은 ADC(Analog-Digital Convertor) 제어보드를이용한 ADC 제어방법및 ADC 제어시스템에관한것으로서, 더욱상세하게는메인보드에구비되는 ADC에입력되는센서신호를미리설정된기준전압과비교하여 ADC에입력되는센서신호에노이즈가개재되었는지여부를판단하는비교기와, 상기비교기를통해감지된노이즈의주기성여부를판단하여상기메인보드에구비되는 CPU로상기 ADC의센서신호취득시점을전송하는 ADC 데이터취득제어부가구비된 ADC 제어보드를이용하여, 센서신호에포함된주기성노이즈의피크(Peak)와피크(Peak) 사이에서 ADC의센서신호취득시점을설정하도록구성함으로써, 경시변화로인한부품이나신호전달라인의열화등의이유로발생되는주기성노이즈의영향을최소화할수 있도록구성된 ADC 제어보드를이용한 ADC 제어방법및 ADC 제어시스템에관한것이다. 이를위하여본 발명은, ADC(Analog-Digital Convertor) 제어보드를이용한 ADC 제어시스템에있어서, 상기 ADC 제어보드는, 메인보드에구비되는 ADC에입력되는센서신호를미리설정된기준전압과비교하여 ADC에입력되는센서신호에노이즈가개재되었는지여부를판단하는비교기; 및상기비교기를통해 ADC에입력되는센서신호에노이즈가개재되었다고판단되는경우, 상기노이즈의주기성여부를판단하여상기메인보드에구비되는 CPU로상기 ADC의센서신호취득시점을전송하는 ADC 데이터취득제어부; 를포함하여구성되되, 상기 ADC 데이터취득제어부는, 상기센서신호에포함된주기성노이즈의피크(Peak)와피크(Peak) 사이에서 ADC의센서신호취득시점을설정하여상기 CPU로전송하는것을특징으로한다.

Abstract translation: 本发明涉及使用模拟数字转换器（ADC）控制板和ADC控制系统的ADC控制方法。 ADC控制板包括一个比较器，用于通过将输入到主板上形成的ADC的传感器信号与预置的参考电压进行比较来确定输入到ADC的传感器信号中是否插入噪声;以及ADC数据采集控制单元， 如果通过比较器确定噪声被插入到输入到ADC的传感器信号中，则通过确定噪声的周期性，传感器信号获取指向在主板上形成的CPU。 本发明使周期性噪声的影响最小化。

公开(公告)号：KR1020120065226A

公开(公告)日：2012-06-20

申请号：KR1020110119910

申请日：2011-11-17

Applicant: 엘지디스플레이 주식회사

Inventor： 강형원

IPC: H03M1/38

CPC classification number: H03M1/462 ,  H03M2201/2291 ,  H03M2201/62 ,  H03M2201/64 ,  H03M2201/83

Abstract: PURPOSE: SAR(Successive Approximation Register) ADC(Analog-Digital Converter) and an analog to digital converting method using the same are provided to maintain an optimized operation speed for resolution by enhancing a response speed of a SAR ADC. CONSTITUTION: A SHA(Sampling/Holding Amplifier)(2) samples and holds an analog voltage inputted from the outside. A comparator(4) outputs a comparison signal according to a comparison result by comparing a level of the held analog voltage and a level of an n bit analog signal. A SAR(Successive Approximation Register) logic circuit(6) successively generates a digital signal from the most significant bit to the least significant bit in response to the comparison signal. A DAC(Digital-Analog Converter)(10) changes the successively outputted digital signal into the n bit analog signal. An output register(8) generates an n bit digital signal by holding digital signals successively outputted from the most significant bit to the least significant bit.

Abstract translation: 目的：提供SAR（逐次逼近寄存器）ADC（模拟数字转换器）和使用其的模数转换方法，以通过提高SAR ADC的响应速度来保持分辨率的优化操作速度。 构成：SHA（取样/保持放大器）（2）采样并保持从外部输入的模拟电压。 比较器（4）通过比较保持的模拟电压的电平和n位模拟信号的电平，根据比较结果输出比较信号。 SAR（连续近似寄存器）逻辑电路（6）响应于比较信号，从最高有效位连续产生数字信号到最低有效位。 DAC（数模转换器）（10）将连续输出的数字信号改变为n位模拟信号。 输出寄存器（8）通过将从最高有效位连续输出的数字信号保持为最低有效位来产生n位数字信号。

公开(公告)号：KR1020100086381A

公开(公告)日：2010-07-30

申请号：KR1020090005729

申请日：2009-01-22

Applicant: (주)에프씨아이

Inventor： 황명운 ,  김영진 ,  문제철 ,  조현하

IPC: H03M1/48 ,  H03M1/12

CPC classification number: H03M1/48 ,  H03M1/18 ,  H03M2201/6107 ,  H03M2201/64

Abstract: PURPOSE: According to the condition automatic following circuit of the analog-digital converter is measurement the signal-noise ratio of the signal of the analog-digital converter and signal of computer signal it best suites, by sweeping the reference voltage although the external environment is used for the other place, the reliability can be offered. CONSTITUTION: The mag signal is when input signal is compared with high-low limit reference voltage created. When compared with the signal of computer signal standard voltage, the signal of computer signal is created The signal-noise ratio measuring unit(30) measures the signal-noise ratio of two inputs signal from the mag signal and the correlator(20) which is input the signal of computer signal of the analog/converter. If it falls less than the fixed threshold, it is enabled and in the control unit(40), the signal-noise ratio signal outputs the sweep signal for the generating reference voltage.

Abstract translation: 目的：根据模拟数字转换器的自动跟随电路测量模拟数字转换器的信号和计算机信号信号的信噪比最好的方法是扫描参考电压，尽管外部环境是 用于另一个地方，可以提供可靠性。 构成：当输入信号与创建的高低限参考电压进行比较时，信号为mag信号。 与计算机信号标准电压信号相比，产生计算机信号信号信噪比测量单元（30）测量来自mag信号的两个输入信号和相关器（20）的信噪比， 输入模拟/转换器的计算机信号信号。 如果它下降到小于固定阈值，则使能，并且在控制单元（40）中，信号噪声比信号输出用于产生参考电压的扫描信号。

公开(公告)号：KR1020090022980A

公开(公告)日：2009-03-04

申请号：KR1020070098091

申请日：2007-09-28

Applicant: 한국전자통신연구원 ,  한양대학교 산학협력단

Inventor： 권오경 ,  김창선 ,  차진종 ,  윤병진

IPC: H03M1/12

CPC classification number: H03M1/0621 ,  H03M1/002 ,  H03M1/802 ,  H03M2201/2233 ,  H03M2201/2291 ,  H03M2201/3178 ,  H03M2201/64

Abstract: A digital-analog converter and an analog-digital converter using the same are provided to obtain an accurate data conversion result by removing the influence of the parasitic capacitance through a virtual ground. A digital-analog converter(1000) includes a first type capacitor array(320) and a second type capacitor array(340), and a charge re-distributor(360). The first and second type capacitor arrays have the different array configuration. The charge re-distributor resets the charge in response to the digital data set in the first and second type capacitor arrays. The charge re-distributor generates the analog voltage corresponding to the electric charge reset result. The first type capacitor array is a weighted capacitor array. The second type capacitor array is a charge sharing capacitor array.

Abstract translation: 提供数模转换器和使用该数模转换器的模数转换器，以通过去除虚拟接地的寄生电容的影响来获得精确的数据转换结果。 数模转换器（1000）包括第一类型电容器阵列（320）和第二类型电容器阵列（340）和电荷再分配器（360）。 第一和第二类型电容器阵列具有不同的阵列配置。 电荷再分配器响应于第一和第二类型电容器阵列中的数字数据而重置电荷。 充电重新分配器产生对应于电荷复位结果的模拟电压。 第一类电容器阵列是加权电容阵列。 第二类电容器阵列是电荷共享电容阵列。

公开(公告)号：KR101531921B1

公开(公告)日：2015-06-30

申请号：KR1020140034578

申请日：2014-03-25

Applicant: 한양대학교 에리카산학협력단

Inventor： 노정진 ,  왕지동

IPC: H03M3/02

CPC classification number: H03M3/366 ,  H03M3/32 ,  H03M3/39 ,  H03M2201/6128 ,  H03M2201/64

Abstract: 본발명은델타-시그마변조기에관한것으로서, 다단적분기피드포워드방식(cascade of integrator feedforward form) 및다단노이즈쉐이핑방식(multi-stage noise-shaping)을이용한델타-시그마변조기에있어서, 입력신호를적분하는제 1 적분기, 상기입력신호의피드포워드신호, 상기제 1 적분기의출력신호, 및상기제 1적분기의피드포워드신호를합산하여적분하는제 2 적분기, 및상기제 2 적분기의출력신호를양자화하는양자화기를포함하고, 상기입력신호의피드포워드신호, 상기제 1 적분기의출력신호, 및상기제 1적분기의피드포워드신호는각각의미분기를거쳐합산되는것을특징으로함으로써, 델타-시그마변조기를간소화할수 있다.

Abstract translation: 本发明涉及一种简化的多位微调Δ-Σ调制器。 在使用级联的积分器前馈形式和多级噪声整形的Δ-Σ调制器中，它包括对输入信号进行积分的第一积分器，将输入信号的前馈信号相加的第二积分器，输入信号的输出信号 第一积分器和第一积分器的前馈信号，以及量化第二积分器的输出信号的量化器。 输入信号的前馈信号，第一积分器的输出信号和第一积分器的前馈信号由每个微分器相加。 从而可以简化Δ-Σ调制。

公开(公告)号：KR1020080046484A

公开(公告)日：2008-05-27

申请号：KR1020060116006

申请日：2006-11-22

Applicant: 삼성전자주식회사

Inventor： 함석헌 ,  이동명 ,  이정환 ,  임승현 ,  한건희

IPC: H03M1/12

CPC classification number: H03M1/1019 ,  H03M1/1023 ,  H03M1/1071 ,  H03M2201/639 ,  H03M2201/64 ,  H03M2201/65

Abstract: An analog-to-digital conversion method is provided to secure a correct analog-to-digital conversion process by modifying upper bits wrongly outputted by parasitic capacitors, a finite voltage gain, noise by a temperature, and a feed-through. An analog-to-digital conversion method includes the steps of: generating a lamp signal corresponding to digital data while changing an upper (N-K) bit of the digital data(S02); comparing a sensed image signal with the lamp signal(S03); determining a value of the upper (N-K) bit of the digital data according to a comparison of the lamp signal and the sensed image signal(S04); generating the lamp signal corresponding to the digital data while changing a lower (K+1) bit of the digital data(S05); comparing a voltage level of the sensed image signal with the sum of the lamp signal and a compensation value(S06); determining a value of a lower K bit of the digital data when the sum of the lamp signal and the compensation value is equal to the voltage level of the sensed image signal(S07); and adjusting the value of the upper (N-K) bit of the digital data according to a most significant 2-bit value of the lower (K+1) bit(S08).

Abstract translation: 提供了一种模数转换方法，用于通过修改由寄生电容器错误输出的高位，有限电压增益，噪声，温度和馈通来确保正确的模数转换过程。 一种模数转换方法包括以下步骤：在改变数字数据的上（N-K）位的同时产生对应于数字数据的灯信号（S02）; 将感测到的图像信号与灯信号进行比较（S03）; 根据灯信号和感测图像信号的比较，确定数字数据的上（N-K）位的值（S04）; 在改变数字数据的较低（K + 1）位的同时，产生与数字数据对应的灯信号（S05）; 将感测图像信号的电压电平与灯信号和补偿值的和进行比较（S06）; 当灯信号和补偿值的总和等于感测图像信号的电压电平时，确定数字数据的较低K位的值（S07）; 并根据较低（K + 1）比特的最高有效2比特值调整数字数据的上（N-K）比特的值（S08）。

公开(公告)号：KR1020060062460A

公开(公告)日：2006-06-12

申请号：KR1020040101312

申请日：2004-12-03

Applicant: 삼성전기주식회사

Inventor： 서승원 ,  백원진 ,  김문선 ,  오승민 ,  나유삼

IPC: H03M3/02

CPC classification number: H03M3/356 ,  H03M3/368 ,  H03M2201/615 ,  H03M2201/64

Abstract: 본 발명은 시그마-델타 변조기의 입력데이터에 랜덤 비트를 더하여 입력함으로써 시그마-델타 변조기의 출력에 나타나는 주기적 성분을 제거하고, 노이즈 레벨을 감소시킬 수 있는 시그마-델타 변조기에 관한 것이다. 본 발명은, 소정의 입력값을 입력받아 (+) 범위에서 (-) 범위 사이의 값을 갖는 비트 스트림을 출력하는 시그마-델타 변조기에 있어서, 소정의 시퀀스로 무작위의 비트를 생성하는 의사 랜덤 비트 시퀀스(PRBS) 생성부; 상기 랜덤 비트 생성 수단에 의해 생성된 무작위의 비트를 상기 시그마-델타 변조기의 입력값과 합산하는 합산기; 및 상기 합산기에 의해 무작위의 비트가 합산된 입력값을 시그마-델타 변조하는 변조회로를 포함하는 시그마-델타 변조기를 제공한다.
시그마-델타 변조기, 프랙셔널(fractional) N 위상 고정 루프(PLL), 의사 랜덤 비스 시퀀스(PRBS)

公开(公告)号：KR1020010083331A

公开(公告)日：2001-09-01

申请号：KR1020000006262

申请日：2000-02-10

Applicant: 삼성전자주식회사

Inventor： 장계언 ,  최광주

IPC: H03M1/34

CPC classification number: H03M1/34 ,  H03M1/06 ,  H03M2201/64

Abstract: PURPOSE: An analog-to-digital converter is provided to minimize an error of a process variable by reducing a number of a capacitor. CONSTITUTION: An analog-to-digital converter includes a first reference voltage generator(22), a second reference voltage generator(24), switches(SW21-SW24,SW40), capacitors(C21,C22), and a comparator(26). The first reference voltage generator(22) responses to a high-ranking 512-bit(D(1024:513)) of digital data provided from an external, performs a partial pressing on a reference voltage(Vref) and a ground voltage(VSS), and outputs the partial pressed first reference voltage(Vmsb). The second reference voltage generator(24) responses to a low-ranking 512-bit(D(512:1)) of digital data provided from the external, performs the partial pressing on a voltage corresponding to 1/4 of the reference voltage(Vref) and a ground voltage(VSS), and outputs the partial pressed second reference voltage(Vlsb). The switch(SW21) is connected between one end of an analog signal(va) inputted from the external and the first capacitor(C21). The switch(SW22) is connected between one end of the first reference voltage(Vmsb) and the first capacitor(C21) outputted from the first reference voltage generator(22). The switch(SW23) is connected between one end of the second reference voltage(Vlsb) and the first capacitor(C22) outputted from the second reference voltage generator(24). The switch(SW24) is connected between one end of the ground voltage(VSS) and the second capacitor(C22).

Abstract translation: 目的：提供模数转换器，通过减少电容器的数量来最小化过程变量的误差。 构成：模数转换器包括第一参考电压发生器（22），第二参考电压发生器（24），开关（SW21-SW24，SW40），电容器（C21，C22）和比较器（26） 。 第一参考电压发生器（22）对从外部提供的数字数据的高位512位（D（1024：513））进行响应，执行对参考电压（Vref）和接地电压（VSS）的部分按压 ），并输出部分按压的第一参考电压（Vmsb）。 第二参考电压发生器（24）对从外部提供的数字数据的低等级的512位（D（512：1））进行响应，对与参考电压的1/4相对应的电压进行部分按压 Vref）和接地电压（VSS），并输出部分按压的第二参考电压（Vlsb）。 开关（SW21）连接在从外部输入的模拟信号（va）的一端与第一电容器（C21）之间。 开关（SW22）连接在第一参考电压（Vmsb）的一端和从第一参考电压发生器（22）输出的第一电容器（C21）之间。 开关（SW23）连接在第二参考电压（Vlsb）的一端和从第二参考电压发生器（24）输出的第一电容器（C22）之间。 开关（SW24）连接在接地电压（VSS）的一端和第二电容器（C22）之间。