公开(公告)号：KR1020040048483A

公开(公告)日：2004-06-10

申请号：KR1020020076230

申请日：2002-12-03

Applicant: 삼성전자주식회사

Inventor： 박문한 ,  임벼리 ,  유재윤

IPC: H01L21/31

CPC classification number: H01L21/28202 ,  H01L21/3144 ,  H01L29/513 ,  H01L29/518

Abstract: PURPOSE: A method for forming a gate oxide layer of a semiconductor device is provided to reduce the proportion of defective devices caused by the formed gate oxide layer by effectively removing the surface contamination of a semiconductor substrate and simultaneously carrying out a nitridation treatment on the gate oxide layer. CONSTITUTION: A cleaning process is carried out for removing a native oxide layer of a semiconductor substrate and an oxide layer generated when removing the native oxide layer(S2). An hydrogen annealing process is carried out on the resultant structure for forming a hydrogen protecting layer, wherein the hydrogen protecting layer is capable of improving the surface roughness of the semiconductor substrate(S4). A gate oxide layer is formed on the resultant structure(S6). A nitridation treatment is carried out on the gate oxide layer for preventing ions from penetrating into the semiconductor substrate(S8).

Abstract translation: 目的：提供一种用于形成半导体器件的栅极氧化层的方法，以通过有效地去除半导体衬底的表面污染物并同时在栅极上进行氮化处理来减少由形成的栅极氧化物层引起的缺陷器件的比例 氧化层。 构成：为了去除半导体衬底的自然氧化物层和去除自然氧化物层而产生的氧化物层，进行清洗处理（S2）。 对形成氢保护层的所得结构进行氢退火处理，其中氢保护层能够改善半导体衬底的表面粗糙度（S4）。 在所得结构上形成栅氧化层（S6）。 在栅极氧化物层上进行氮化处理，以防止离子渗入半导体衬底（S8）。

公开(公告)号：KR1020030087672A

公开(公告)日：2003-11-15

申请号：KR1020020025511

申请日：2002-05-09

Applicant: 삼성전자주식회사

Inventor： 박문한 ,  권대진 ,  유재윤

IPC: H01L21/8247

Abstract: PURPOSE: A method for manufacturing a non-volatile memory device is provided to be capable of preventing the contact between a nitride layer and a gate polysilicon layer. CONSTITUTION: After sequentially forming the first oxide layer(12), a silicon nitride layer(14), and the second oxide layer(16) on a semiconductor substrate(10), a gate electrode formation region is defined by carrying out a photo and etching process for selectively exposing the upper surface of the semiconductor substrate. A silicon layer is partially grown at the exposed portion of the semiconductor substrate for preventing the contact with the silicon nitride layer. An oxide layer(32) is formed at the resultant structure by carrying out a gate oxidation process. Then, a gate polysilicon layer(34) is formed at the upper portion of the oxide layer.

Abstract translation: 目的：提供一种用于制造非易失性存储器件的方法，以能够防止氮化物层和栅极多晶硅层之间的接触。 构成：在顺序地形成第一氧化物层（12）之后，在半导体衬底（10）上形成氮化硅层（14）和第二氧化物层（16），通过执​​行照片和 用于选择性地暴露半导体衬底的上表面的蚀刻工艺。 在半导体衬底的暴露部分部分地生长硅层，以防止与氮化硅层的接触。 通过进行栅极氧化处理，在所得结构处形成氧化物层（32）。 然后，在氧化物层的上部形成栅多晶硅层（34）。

公开(公告)号：KR100375229B1

公开(公告)日：2003-03-08

申请号：KR1020000039317

申请日：2000-07-10

Applicant: 삼성전자주식회사

Inventor： 이한신 ,  박문한

IPC: H01L21/76

CPC classification number: H01L21/76224

Abstract: In a trench isolation method, an etching mask pattern for forming a trench is formed on a semiconductor substrate. The substrate is etched to form a trench. An insulating layer is formed to fill the trench, and then a material layer is formed on the insulating layer. In this case, the material layer is made of material formed at a high temperature to density the insulating layer. The material layer and the insulating layer are planarly etched and the etching mask pattern is removed, so that a trench isolation layer is completed. Accordingly, although a densification process is avoided, it is possible to form a device isolation layer having a favorable surface profile.

Abstract translation: 在沟槽隔离方法中，在半导体衬底上形成用于形成沟槽的蚀刻掩模图案。 衬底被蚀刻以形成沟槽。 形成绝缘层以填充沟槽，然后在绝缘层上形成材料层。 在这种情况下，材料层由在高温下形成的材料制成以密度绝缘层。 平面蚀刻材料层和绝缘层并去除蚀刻掩模图案，从而完成沟槽隔离层。 因此，尽管避免了致密化过程，但可以形成具有有利表面轮廓的器件隔离层。

公开(公告)号：KR1020020071169A

公开(公告)日：2002-09-12

申请号：KR1020010011142

申请日：2001-03-05

Applicant: 삼성전자주식회사

Inventor： 홍수진 ,  박문한 ,  구주선 ,  허진화 ,  김홍근 ,  홍은기

IPC: H01L21/76

CPC classification number: H01L21/76224

Abstract: PURPOSE: A method of forming an insulation layer in trench isolation type semiconductor device is provided to fill isolation layer into a trench having a high aspect ratio without defects by using an SOG(Spin On glass) layer. CONSTITUTION: A trench etch mask pattern(13) is formed on a substrate(10) including a pad oxide layer(11). A trench for isolation is formed on the substrate(10) by etching the substrate(10). A thermal oxide layer(15) is formed on an inner wall of the trench. A silicon nitride liner(17) is laminated on the thermal oxide layer(15). An SOG layer is formed on the substrate(10). A curing process for the SOG layer is performed. An etch process for the cured SOG layer(211) is performed. A silicon oxide layer(31) is deposited on the substrate(10) by a CVD(Chemical Vapor Deposition) method. A trench isolation layer is formed by removing the silicon nitride layer and the pad oxide layer(11).

Abstract translation: 目的：提供一种在沟槽隔离型半导体器件中形成绝缘层的方法，通过使用SOG（旋转玻璃）层将隔离层填充到具有高纵横比的无沟槽的沟槽中。 构成：在包括衬垫氧化物层（11）的衬底（10）上形成沟槽蚀刻掩模图案（13）。 通过蚀刻基板（10）在基板（10）上形成用于隔离的沟槽。 在该沟槽的内壁上形成热氧化层（15）。 氮化硅衬垫（17）层压在热氧化物层（15）上。 在基板（10）上形成SOG层。 执行SOG层的固化过程。 执行固化的SOG层（211）的蚀刻工艺。 通过CVD（化学气相沉积）方法将氧化硅层（31）沉积在衬底（10）上。 通过去除氮化硅层和衬垫氧化物层（11）形成沟槽隔离层。

公开(公告)号：KR100338767B1

公开(公告)日：2002-05-30

申请号：KR1019990043989

申请日：1999-10-12

Applicant: 삼성전자주식회사

Inventor： 박태서 ,  박문한 ,  박경원 ,  이한신

IPC: H01L21/76

CPC classification number: H01L21/76235

Abstract: 트렌치상부코너를라운딩하고이 부분에서의산화량을증대시켜트랜지스터의험프및 역방향협폭현상을개선한트렌치소자분리구조와이러한구조를갖는반도체소자및 트렌치소자분리방법이개시되어있다. 그트렌치소자분리방법은, 반도체기판의비활성영역에트렌치를형성하는단계와, 트렌치의내벽에, 10 ∼ 150Å두께의내벽산화막을형성하는단계와, 내벽산화막을덮는라이너(liner)를형성하는단계, 및트렌치를절연막으로매립하는단계를포함하여이루어진다.

公开(公告)号：KR100322531B1

公开(公告)日：2002-03-18

申请号：KR1019990019023

申请日：1999-05-26

Applicant: 삼성전자주식회사

Inventor： 김성의 ,  이금주 ,  황인석 ,  고용선 ,  안동호 ,  박문한 ,  박태서

IPC: H01L21/76

CPC classification number: H01L21/76224

Abstract: 트랜치소자분리공정에서질화막으로이루어진라이너층을사용하면서도덴트(Dent)의발생을억제할수 있는반도체소자의트랜치소자분리방법및 이를이용한반도체소자에관해개시한다. 이를위해본 발명은질화막으로이루어진라이너층을형성하기전에산화막으로된 파임방지막을추가로형성하거나, 산화막과질화막의복합막으로된 복합라이너층을구성하여질화막으로된 마스크패턴을제거할때에라이너층에서발생하는덴트(Dent)의발생을억제한다. 상기파임방지용산화막이단일막인경우에는화학기상증착에의한산화막을증착하여사용하거나, 실리콘막을증착한후 이를열산화시킨산화막을사용한다. 또한, 상기파임방지막이복합라이너층인경우에는질화막과산화막혹은산화막과질화막이적어도 1회이상순차적으로적층된구조의복합막을사용한다.

公开(公告)号：KR1020010111779A

公开(公告)日：2001-12-20

申请号：KR1020000032445

申请日：2000-06-13

Applicant: 삼성전자주식회사

Inventor： 박태서 ,  박문한 ,  홍수진

IPC: H01L21/76

Abstract: 트렌치 소자분리 방법이 제공된다. 이 방법은 반도체기판 상에 반도체기판의 소정영역을 노출시키는 패드질화막 패턴을 형성하고, 노출된 반도체기판을 식각하여 활성영역을 한정하는 트렌치 영역을 형성한다. 트렌치 영역이 형성된 결과물을 열산화시키어 트렌치 영역의 측벽 및 바닥에 열산화막을 형성한다. 여기서, 패드질화막 패턴은 반도체기판과 직접 접촉하거나 이들 사이에 50Å 이하의 얇은 패드산화막 패턴을 형성시키어 트렌치 영역의 상부 모서리 부분에 패드질화막 패턴에 기인하는 인장 스트레스를 가한다. 이에 따라, 트렌치 영역의 상부 모서리 부분에 형성되는 열산화막은 다른 부분의 열산화막에 비하여 두껍게 형성된다. 열산화막에 의해 둘러싸여진 트렌치 영역 내에 소자분리막을 형성하고, 패드질화막 패턴을 제거하여 활성영역을 노출시킨다. 노출된 활성영역 상에 게이트 산화막을 형성한다.

公开(公告)号：KR100304688B1

公开(公告)日：2001-11-30

申请号：KR1019940003979

申请日：1994-02-28

Applicant: 삼성전자주식회사

Inventor： 김영욱 ,  박문한 ,  이내인 ,  오관영

IPC: H01L21/28

Abstract: PURPOSE: A fabrication method of semiconductor devices is provided to improve a reliability of the device by removing F(Fluorine) elements from a tungsten silicide layer after removing contaminated materials on the surface of the tungsten silicide layer and performing a thermal treatment. CONSTITUTION: An oxide(11) is formed on a substrate(10) by a thermal oxidation. A polysilicon layer(12) is formed on the entire surface of the resultant structure. A tungsten silicide layer(13) is formed on the polysilicon layer(12) by CVD(Chemical Vapour Deposition) using WF6 and SiH4 as a reaction gas. At this time, contaminated materials are removed from the tungsten silicide layer(13). Fluorine elements are then removed from the tungsten silicide layer(13) to the free surface of the tungsten silicide layer(13) by an outdiffusion through a thermal treatment.

公开(公告)号：KR1020010036818A

公开(公告)日：2001-05-07

申请号：KR1019990043991

申请日：1999-10-12

Applicant: 삼성전자주식회사

Inventor： 안동호 ,  박문한

IPC: H01L21/76

Abstract: PURPOSE: A method for forming a T-shaped trench isolation layer is provided to prevent degradation of device reliability due to an opened void. CONSTITUTION: In the method, the first trench is formed in a substrate(110) by using a mask pattern(120). The mask pattern(120) is composed of a gate oxide layer(122), a polysilicon layer(124), a silicon nitride layer(126) and a silicon oxide layer(128). Then, an insulating spacer is formed on sidewalls of the first trench and the mask pattern(120). Thereafter, the substrate(110) is etched again by using both the insulating spacer and the mask pattern(120) as an etching mask, so that the second trench is formed narrower and deeper than the first trench. The second trench is then filled with an insulating material to obtain the T-shaped trench isolation layer(I).

Abstract translation: 目的：提供一种用于形成T形沟槽隔离层的方法，以防止由于开放的空隙导致的器件可靠性的劣化。 构成：在该方法中，通过使用掩模图案（120）将第一沟槽形成在衬底（110）中。 掩模图案（120）由栅极氧化物层（122），多晶硅层（124），氮化硅层（126）和氧化硅层（128）组成。 然后，在第一沟槽和掩模图案（120）的侧壁上形成绝缘间隔物。 此后，通过使用绝缘间隔物和掩模图案（120）作为蚀刻掩模再次蚀刻衬底（110），使得第二沟槽形成为比第一沟槽更窄和更深。 然后用绝缘材料填充第二沟槽，以获得T形沟槽隔离层（I）。

公开(公告)号：KR1020000077020A

公开(公告)日：2000-12-26

申请号：KR1020000018901

申请日：2000-04-11

Applicant: 삼성전자주식회사

Inventor： 박태서 ,  박문한 ,  박경원 ,  이한신 ,  김정엽 ,  홍창기 ,  강호규 ,  김성의 ,  홍수진

IPC: H01L21/76

CPC classification number: C09G1/02 ,  C09K3/1463 ,  H01L21/31053 ,  H01L21/76224

Abstract: PURPOSE: A trench isolation method is provided to simplify a manufacturing process and reduce an aspect ratio in filling a trench as compared with a shallow trench isolation(STI) method by using a photoresist pattern as a mask for forming the trench, and to uniformly maintain chemical mechanical polishing(CMP) quantity for forming an isolation layer of a uniform thickness by using CeO2 based polishing agent having a large CMP selectivity of a silicon substrate and an oxidation layer. CONSTITUTION: A photoresist pattern is formed on a side of a bare silicon substrate(100). A predetermined depth of the substrate is etched to form a trench by using the photoresist pattern as an etching mask. The photoresist pattern is eliminated. An insulating layer is formed in the trench. A chemical mechanical polishing(CMP) process is performed regarding the resultant structure having the insulating layer by using slurry including CeO2 based polishing agent until the substrate is exposed.

Abstract translation: 目的：提供沟槽隔离方法，以便通过使用光致抗蚀剂图案作为形成沟槽的掩模，与浅沟槽隔离（STI）方法相比，简化制造工艺并缩小填充沟槽的纵横比，并且均匀地保持 通过使用具有大的CMP选择性的硅衬底和氧化层的CeO 2基抛光剂形成均匀厚度的隔离层的化学机械抛光（CMP）量。 构成：在裸硅衬底（100）的一侧上形成光致抗蚀剂图案。 通过使用光致抗蚀剂图案作为蚀刻掩模来蚀刻衬底的预定深度以形成沟槽。 消除光致抗蚀剂图案。 在沟槽中形成绝缘层。 通过使用包含CeO 2的研磨剂的浆料直到基材露出，对具有绝缘层的所得结构进行化学机械抛光（CMP）工艺。