公开(公告)号：GB2616573B

公开(公告)日：2025-02-19

申请号：GB202309314

申请日：2021-10-21

Applicant: IBM

Inventor： YOUNGSEOK KIM ,  CHOONGHYUN LEE ,  TIMOTHY MATHEW PHILIP ,  SOON-CHEON SEO ,  INJO OK ,  ALEXANDER REZNICEK

IPC: G11C11/00 ,  G11C13/00 ,  H10B63/00 ,  H10N70/20

Abstract: A vertical resistive memory array is presented. The array includes a pillar electrode and a switching liner around the side perimeter of the pillar electrode. The array includes two or more vertically stacked single cell (SC) electrodes connected to a first side of the switching liner. The juxtaposition of the switching liner, the pillar electrode, and each SC electrode forms respective resistance switching cells (e.g., OxRRAM cell). A vertical group or bank of these cells may be connected in parallel and each share the same pillar electrode. The cells in the vertical cell bank may written to or read from as a group to limit the effects of inconsistent CF formation of any one or more individual cells within the group.

公开(公告)号：IL298029A

公开(公告)日：2023-01-01

申请号：IL29802922

申请日：2022-11-07

Applicant: IBM CORP ,  TAO LI ,  TSUNG SHENG KANG ,  RUILONG XIE ,  ALEXANDER REZNICEK ,  OLEG GLUSCHENKOV

Inventor： TAO LI ,  TSUNG-SHENG KANG ,  RUILONG XIE ,  ALEXANDER REZNICEK ,  OLEG GLUSCHENKOV

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/3065 ,  H01L21/74 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L23/535 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/45 ,  H01L29/66 ,  H01L29/786

Abstract: Semiconductor device designs having a buried power rail with a sloped epitaxy buried contact are provided. In one aspect, a semiconductor FET device includes: at least one gate disposed on a substrate; source and drains on opposite sides of the at least one gate, wherein at least one of the source and drains has a sloped surface; a buried power rail embedded in the substrate; and a buried contact that connects the buried power rail to the sloped surface of the at least one source and drain. Sidewall spacers separate the buried power rail from the substrate. A top of the sloped surface of the at least one source and drain is above a top surface of the buried contact. Methods of forming a semiconductor FET device are also provided.

公开(公告)号：GB2607792A

公开(公告)日：2022-12-14

申请号：GB202212342

申请日：2021-01-05

Applicant: IBM

Inventor： YASIR SULEHRIA ,  ALEXANDER REZNICEK ,  OLEG GLUSCHENKOV ,  DEVIKA SIL

IPC: H01L43/08

Abstract: Large grain metal bitlines are formed above magnetic tunnel junction pillars used as MRAM bits without materially affecting the magnetic properties of the magnetic tunnel junctions. A copper or copper alloy bitline having relatively small grains is formed over the pillars. Laser annealing is employed to melt the bitline. Subsequent cooling and recrystallization results in a reduction of the number of grain boundaries in the bitline and a reduction in bitline effective resistivity. Multiple melt/cool cycles may be used. Bitline grains are vertically aligned with the pillars in a resulting structure.

公开(公告)号：GB2603591A

公开(公告)日：2022-08-10

申请号：GB202116915

申请日：2021-11-24

Applicant: IBM

Inventor： TAKASHI ANDO ,  ALEXANDER REZNICEK ,  POUYA HASHEMI ,  RUILONG XIE

IPC: H01L45/00 ,  G11C13/00

Abstract: A cross-bar ReRAM comprising: a substrate 205; a plurality of first columns extending from the substrate and containing a ReRAM stack 220, 225, 230, 226, 221; a plurality of second columns 250, 255 extending perpendicular to the first columns, and located on top of the first columns such that they cross over the first columns; and, a dielectric layer 245 filling the space between the first and the second columns, wherein the dielectric layer is in direct contact with a sidewall of each layer of the ReRAM stack. ReRAM stack layers 220 & 221 may comprise TaN, layers 225 & 226 may comprise TiN and layer 230 may comprise HfO2. Each column may comprise a metal liner with a metal layer formed thereon. The ReRAM stack may be in direct contact with the second column. A logic circuit may be formed at the same time as the ReRAM array.

公开(公告)号：GB2599523A

公开(公告)日：2022-04-06

申请号：GB202117805

申请日：2020-04-06

Applicant: IBM

Inventor： ALEXANDER REZNICEK ,  JENG-BANG YAU ,  BAHMAN HEKMATSHOARTABARI

IPC: G01N27/414 ,  H01L29/73

Abstract: A biosensor includes a bulk silicon substrate and a vertical bipolar junction transistor (BJT) formed on at least a portion of the substrate. The BJT includes an emitter region, a collector region and an epitaxially grown intrinsic base region between the emitter and collector regions. The biosensor further includes a sensing structure formed on at least a portion of two vertical surfaces of the intrinsic base region of the BJT. The sensing structure includes a channel/trench opening, exposing the intrinsic base region on at least first and second opposing sides thereof, and at least one dielectric layer formed in the channel/trench opening and contacting at least a portion of the intrinsic base region, the dielectric layer being configured to respond to charges in biological molecules.

公开(公告)号：GB2591186B

公开(公告)日：2022-01-05

申请号：GB202102153

申请日：2019-07-18

Applicant: IBM

Inventor： TAKASHI ANDO ,  ALEXANDER REZNICEK ,  POUYA HASHEMI

IPC: H01L21/336 ,  H01L27/24

Abstract: A semiconductor structure includes an oxide ReRAM co-integrated with a drain region of a field effect transistor (FET). The oxide ReRAM has a tip region defined by a pointed cone that contacts a faceted upper surface of the drain region of the FET. Such a tip region enhances the electric field of the oxide ReRAM and thus helps to control forming of the conductive filament of the oxide ReRAM.

公开(公告)号：GB2591186A

公开(公告)日：2021-07-21

申请号：GB202102153

申请日：2019-07-18

Applicant: IBM

Inventor： ALEXANDER REZNICEK ,  TAKASHI ANDO ,  POUYA HASHEMI

IPC: H01L21/336

Abstract: A semiconductor structure includes an oxide Re RAM co-integrated with a drain region of a field effect transistor (FET). The oxide Re RAM has a tip region defined by a pointed cone that contacts a faceted upper surface of the drain region of the FET. Such a tip region enhances the electric field of the oxide Re RAM and thus helps to control forming of the conductive filament of the oxide Re RAM.

公开(公告)号：GB2550740B

公开(公告)日：2020-05-20

申请号：GB201712260

申请日：2016-01-04

Applicant: IBM

Inventor： BRUCE DORIS ,  KERN RIM ,  ALEXANDER REZNICEK ,  DARSEN DUANE LU ,  ALI KHAKIFIROOZ ,  KANGGUO CHENG

IPC: H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L29/66

Abstract: A method for fabricating a semiconductor device, includes providing a strained silicon on insulator (SSOI) structure, the SSOI structure comprises, a dielectric layer disposed on a substrate, a silicon germanium layer disposed on the dielectric layer, and a strained semiconductor material layer disposed directly on the silicon germanium layer, forming a plurality of fins on the SSOI structure, forming a gate structure over a portion of at least one fin in a nFET region, forming a gate structure over a portion of at least one fin in a pFET region, removing the gate structure over the portion of the at least one fin in the pFET region, removing the silicon germanium layer exposed by the removing, and forming a new gate structure over the portion of the at least one fin in the pFET region, such that the new gate structure surrounds the portion on all four sides.