公开(公告)号：WO2005004206A3

公开(公告)日：2005-02-17

申请号：PCT/US2004021279

申请日：2004-06-30

Applicant: IBM ,  BRYANT ANDRES ,  CLARK WILLIAM F ,  FRIED DAVID M ,  JAFFE MARK D ,  NOWAK EDWARD J ,  PEKARIK JOHN J ,  PUTNAM CHRISTOPHER S

Inventor： BRYANT ANDRES ,  CLARK WILLIAM F ,  FRIED DAVID M ,  JAFFE MARK D ,  NOWAK EDWARD J ,  PEKARIK JOHN J ,  PUTNAM CHRISTOPHER S

IPC: H01L21/308 ,  H01L21/336 ,  H01L21/84 ,  H01L27/12 ,  H01L29/786 ,  H01L29/06 ,  H01L21/00 ,  H01L21/8238 ,  H01L29/76

CPC classification number: H01L21/84 ,  H01L21/3086 ,  H01L21/3088 ,  H01L27/1203 ,  H01L29/66795 ,  H01L29/785 ,  Y10S438/947

Abstract: A method and structure for an integrated circuit structure that utilizes complementary fin-type field effect transistors (FinFETs) is disclosed. The invention has a first-type of FinFET which includes a first fin (100), and a second-type of FinFET which includes a second fin (102) running parallel to the first fin (100). The invention also has an insulator fin positioned between the source/drain regions (130) of the first first-type of FinFET and the second-type of FinFET. The insulator fin has approximately the same width dimensions as the first fin (100) and the second fin (102), such that the spacing between the first-type of FinFET and the second-type of FinFET is approximately equal to the width of one fin. The invention also has a common gate (106) formed over channel regions of the first-type of FinFET and the second-type of FinFET. The gate (106) includes a first impurity doping region adjacent the first-type of FinFET and a second impurity doping region adjacent the second-type of FinFET. The differences between the first impurity doping region and the second impurity doping region provide the gate with different work functions related to differences between the first-type of FinFET and the second-type of FinFET. The first fin (100) and the second fin (102) have approximately the same width.

Abstract translation: 公开了一种利用互补鳍型场效应晶体管（FinFET）的集成电路结构的方法和结构。 本发明具有包括第一鳍片（100）的第一类型FinFET以及包括平行于第一鳍片（100）延伸的第二鳍片（102）的第二类型FinFET。 本发明还具有位于第一第一类型FinFET的源极/漏极区域（130）与第二类型FinFET之间的绝缘体鳍状物。 绝缘体鳍状物具有与第一鳍状物（100）和第二鳍状物（102）大致相同的宽度尺寸，使得第一类型的FinFET和第二类型的FinFET之间的间隔大致等于一个 鳍。 本发明还具有在第一类型FinFET和第二类型FinFET的沟道区上形成的共同栅极（106）。 栅极（106）包括与第一类型FinFET相邻的第一杂质掺杂区域和与第二类型FinFET相邻的第二杂质掺杂区域。 第一杂质掺杂区域和第二杂质掺杂区域之间的差异为栅极提供与第一类型的FinFET和第二类型的FinFET之间的差异有关的不同的功函数。 第一翅片（100）和第二翅片（102）具有大致相同的宽度。

公开(公告)号：GB2503806B

公开(公告)日：2016-03-09

申请号：GB201311356

申请日：2013-01-28

Applicant: IBM

Inventor： NOWAK EDWARD J ,  ANDERSON BRENT ALAN ,  BRYANT ANDRES

IPC: H01L29/66 ,  H01L29/78

Abstract: A fin field effect transistor (FinFET) structure and method of making the FinFET including a silicon fin that includes a channel region and source/drain (S/D) regions, formed on each end of the channel region, where an entire bottom surface of the channel region contacts a top surface of a lower insulator and bottom surfaces of the S/D regions contact first portions of top surfaces of a lower silicon germanium (SiGe) layer. The FinFET structure also includes extrinsic S/D regions that contact a top surface and both side surfaces of each of the S/D regions and second portions of top surfaces of the lower SiGe layer. The FinFET structure further includes a replacement gate or gate stack that contacts a conformal dielectric, formed over a top surface and both side surfaces of the channel region.

公开(公告)号：GB2499314A

公开(公告)日：2013-08-14

申请号：GB201301434

申请日：2013-01-28

Applicant: IBM

Inventor： NOWAK EDWARD ,  ANDERSON BRENT ALAN ,  BRYANT ANDRES

IPC: H01L29/78 ,  H01L29/66

Abstract: A fin field effect transistor (FinFET) structure and method of making the FinFET including a silicon fin that includes a channel region 154 and source/drain (S/D) regions 156, formed on each end of the channel region 154, where an entire bottom surface of the channel region 154 contacts a top surface of a lower insulator 722 and bottom surfaces of the S/D regions 156 contact first portions of top surfaces of a lower silicon germanium (SiGe) layer 120; the FinFET structure also includes extrinsic S/D regions 456 that contact a top surface and both side surfaces of each of the S/D regions 156 and second portions of top surfaces of the lower SiGe layer 120; the FinFET structure further includes a replacement gate or gate stack 884 that contacts a conformal dielectric 882, formed over a top surface and both side surfaces of the channel region 154, that is disposed above the lower insulator 722 and not above the first and second portions of the lower SiGe layer 120, in which the gate stack 884 is electrically insulated from the extrinsic S/D regions by the conformal dielectric. Also disclosed is a similar FinFET were the SiGe layer 120 is replaced with an insulating material.

公开(公告)号：DE10296953T5

公开(公告)日：2004-04-29

申请号：DE10296953

申请日：2002-06-06

Applicant: IBM

Inventor： BRYANT ANDRES ,  IEONG MEIKEI ,  MULLER K PAUL ,  NOWAK EDWARD J ,  FRIED DAVID M ,  RANKIN JED

IPC: H01L21/336 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L21/28

Abstract: A method for forming a transistor. A semiconductor substrate is provided. The semiconductor substrate is patterned to provide a first body edge. A first gate structure of a first fermi level is provided adjacent the first body edge. The semiconductor substrate is patterned to provide a second body edge. The first and second body edges of the semiconductor substrate define a transistor body. A second gate structure of a second fermi level is provided adjacent the second body edge. A substantially uniform dopant concentration density is formed throughout the transistor body.

公开(公告)号：HK1026064A1

公开(公告)日：2000-12-01

申请号：HK00105169

申请日：2000-08-17

Applicant: IBM

Inventor： BRYANT ANDRES ,  CLARK WILLIAM F ,  ELLIS-MONAGHAN JOHN J ,  MACIEJEWSKI EDWARD P ,  NOWAK EDWARD J ,  PRICER WILBUR D ,  TONG MINH H

IPC: H01L27/06 ,  H01L21/8234 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L

Abstract: A device design for an FET in SOI CMOS which is designed for enhanced avalanche multiplication of current through the device when the FET is on, and to remove the body charge when the FET is off. The FET has an electrically floating body and is substantially electrically isolated from the substrate. The present invention provides a high resistance path coupling the floating body of the FET to the source of the FET, such that the resistor enables the device to act as a floating body for active switching purposes and as a grounded body in a standby mode to reduce leakage current. The high resistance path has a resistance of at least 1 M-ohm, and comprises a polysilicon resistor which is fabricated by using a split polysilicon process in which a buried contact mask opens a hole in a first polysilicon layer to allow a second polysilicon layer to contact the substrate.

公开(公告)号：GB2498621A

公开(公告)日：2013-07-24

申请号：GB201221477

申请日：2012-11-29

Applicant: IBM

Inventor： BRYANT ANDRES ,  NOWAK EDWARD ,  ANDERSON BRENT ALAN ,  ADKISSON JAMES WILLIAM

IPC: H01L29/66 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8232 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/423

Abstract: In a method of forming an integrated circuit structure, a first compensating implant (Fig. 2; 120) with opposite dopant polarity to the semiconductor channel implant (Fig. 1; 114) is implanted uniformly into a substrate for example a silicon on insulator (SOI) substrate, to a depth shallower than a semiconductor channel implant depth. A mask 130 is patterned on the first compensating implant 122 in the substrate, including an opening 138 exposing a channel location of the substrate. A second compensating implant 140 called an anti-halo implant has doping polarity the same as the channel implant polarity, and is implanted into the channel location through the mask opening in the channel location and at an angle offset from perpendicular to the top surface of the substrate. The second compensating implant 142 is particularly useful for long channel transistors. It is positioned closer to a first side of the channel location relative to an opposite second side of the channel location. A gate insulator layer 132 and gate conductor (Fig. 5; 152) are formed above the channel location of the substrate in the mask opening 138. The mask is removed to leave the gate conductor standing on the channel location of the substrate. Source and drain extension regions (Fig. 6; 162) are formed by implanting using the gate structure as a mask, after which gate sidewalls (Fig. 7; 170) are formed and source and drain implants (Fig. 7; 174, 176) are implanted using the gate sidewalls as masks. The width of the anti-halo implant 142 is automatically matched to the width of gate.

公开(公告)号：MY124337A

公开(公告)日：2006-06-30

申请号：MYPI9903693

申请日：1999-08-27

Applicant: IBM

Inventor： BRYANT ANDRES ,  NOWAK EDWARD J ,  TONG MINH H

IPC: H01L21/335 ,  H01L27/01 ,  H01L21/84 ,  H01L27/02 ,  H01L27/12 ,  H01L29/10

Abstract: AN SOI PASS-GATE DISTURB SOLUTION FOR AN N-TYPE MOSFET (30) WHEREIN A RESISTOR (70) IS CONNECTED BETWEEN THE GATE (60) AND THE BODY (40) OF THE FET TO ELIMINATE THE DISTRUB CONDITION . THE FET (100) IS FABRICATED INA SUBSTRATE HAVING A SOURCE (211), A DRAIN (212) AND A GATE (112), WHEREIN THE BODY (108) OF THE FIELD EFFECT TRANSISTOR IS ELECTRICALLY FLOATING AND THE TRANSISTOR IS SUBSTANTIALLY ELECTRICALLY ISOLATED FROM THE SUBSTRATE. A HIGH RESISTANCE PATH (119) IS PROVIDED COUPLING THE ELECTRICALLY FLOATING BODY OF THE FET TO THE GATE, SUCH THAT THE BODY DISCHARGES TO A LOW STATE BEFORE SIGNIFICANT THERMAL CHARGING CAN OCCUR WHEN THE GATE IS LOW, AND THUS PREVENTS THE ACCUMULATION OF A CHARGE ON THE BODY WHEN THE TRANSISTOR IS OFF. THE RESISTANCE OF THE HIGH RESISTANCE PATH IS PREFERABLY APPROXIMATELY 10(10) OHMS-UM DIVIDED BY THE WIDTH OF THE PASS-GATE.FIGURE 2

公开(公告)号：DE102013201035B4

公开(公告)日：2017-07-13

申请号：DE102013201035

申请日：2013-01-23

Applicant: IBM

Inventor： ANDERSON BRENT A ,  BRYANT ANDRES ,  NOWAK EDWARD J

IPC: H01L29/78 ,  H01L21/336

Abstract: Finnen-Feldeffekttransistor(FinFET)-Struktur, die aufweist: eine Siliciumfinne (152), die einen Kanalbereich (154) und Source/Drain(S/D)-Bereiche (156) aufweist, die an jedem Ende des Kanalbereichs ausgebildet sind, wobei eine gesamte untere Fläche des Kanalbereichs und untere Flächen von Abschnitten der S/D-Bereiche, die an den Kanalbereich angrenzen, mit einer oberen Fläche eines unteren Isolators (722) in Kontakt stehen und untere Flächen von weiteren Abschnitten der S/D-Bereiche, die an die Abschnitte der S/D-Bereiche angrenzen, mit ersten Abschnitten von oberen Flächen einer unteren Silicium-Germanium(SiGe)-Schicht (120) in Kontakt stehen; extrinsische S/D-Bereiche (456), die mit einer oberen Fläche und beiden seitlichen Flächen jedes der S/D-Bereiche und zweiten Abschnitten von oberen Flächen der unteren SiGe-Schicht in Kontakt stehen; einen Gate-Stapel (884), der mit einem konformen Dielektrikum (882) in Kontakt steht, das über einer oberen Fläche und beiden seitlichen Flächen des Kanalbereichs ausgebildet ist und das über dem unteren Isolator und nicht über den ersten und zweiten Abschnitten der unteren SiGe-Schicht angeordnet ist, wobei der Gate-Stapel durch das konforme Dielektrikum von den extrinsischen S/D-Bereichen elektrisch getrennt ist, wobei eine obere Fläche des unteren Isolators und die obere Fläche der unteren SiGe-Schicht koplanar sind, wobei der untere Isolator und die untere SiGe-Schicht auf einem kristallinen Si-Substrat (110) ausgebildet sind.

公开(公告)号：GB2511445B

公开(公告)日：2015-11-25

申请号：GB201408705

申请日：2012-12-24

Applicant: IBM

Inventor： BRYANT ANDRES ,  BASKER VEERARAGHAVAN S ,  BU HUIMING ,  LEOBANDUNG EFFENDI ,  HAENSCH WILFRIED ,  LIN CHUNG-HSUN ,  STANDAERT THEORDORUS E ,  YAMASHITA TENKO ,  YEH CHUN-CHEN

IPC: H01L29/417 ,  H01L29/66

公开(公告)号：DE102012222265A1

公开(公告)日：2013-06-20

申请号：DE102012222265

申请日：2012-12-05

Applicant: IBM

Inventor： BRYANT ANDRES ,  ANDERSON BRENT A ,  NOWAK EDWARD J ,  ADKISSON JAMES W

IPC: H01L21/336 ,  H01L27/105

Abstract: In einem Verfahren zum Ausbilden einer integrierten Schaltungsstruktur wird eine erste Kompensationsimplantation in ein Substrat implantiert. Bei dem Verfahren wird eine Maske auf der ersten Kompensationsimplantation in dem Substrat strukturiert. Die Maske beinhaltet eine Öffnung, die eine Kanalposition des Substrats freilegt. In dem Verfahren wird eine zweite Kompensationsimplantation in die Kanalposition des Substrats implantiert. Die zweite Kompensationsimplantation wird durch die Öffnung in der Maske und in einem Winkel durchgeführt, der von der Senkrechten zu der oberen Fläche des Substrats versetzt ist. Die zweite Kompensationsimplantation wird näher an einer ersten Seite der Kanalposition im Verhältnis zu einer gegenüberliegenden zweiten Seite der Kanalposition positioniert, und die zweite Kompensationsimplantation weist ein Material auf, das über dieselbe Dotierungspolarität wie die Halbleiter-Kanalimplantation verfügt. Anschließend wird in dem Verfahren ein Gate-Leiter über der Kanalposition des Substrats in der Öffnung der Maske ausgebildet. Als Nächstes wird in dem Verfahren die Maske entfernt, sodass der Gate-Leiter auf der Kanalposition des Substrats stehend zurückbleibt. In dem Verfahren werden Source- und Drain-Implantationen in Source/Drain-Bereiche des Substrats (die an die Kanalposition angrenzen) implantiert.