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    Modularized three-dimensional capacitor array
    21.
    发明专利
    Modularized three-dimensional capacitor array 未知

    公开(公告)号：GB2504032B

    公开(公告)日：2014-06-25

    申请号：GB201318585

    申请日：2010-08-23

    Applicant: IBM

    Inventor： HSU LOUIS LU-CHEN ,  OUYANG XU ,  YANG CHIH-CHAO

    IPC: H01L27/06

    Abstract: A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.

    Modularized three-dimensional capacitor array
    22.
    发明专利
    Modularized three-dimensional capacitor array 未知

    公开(公告)号：GB2486115A

    公开(公告)日：2012-06-06

    申请号：GB201204298

    申请日：2010-08-23

    Applicant: IBM

    Inventor： HSU LOUIS LU-CHEN ,  OUYANG XU ,  YANG CHIH-CHAO

    IPC: G11C11/24 ,  G11C11/34

    Abstract: A modularized capacitor array includes a plurality of capacitor modules. Each capacitor module includes a capacitor and a switching device that is configured to electrically disconnect the capacitor. The switching device includes a sensing unit configured to detect the level of leakage of the capacitor so that the switching device disconnects the capacitor electrically if the leakage current exceeds a predetermined level. Each capacitor module can include a single capacitor plate, two capacitor plates, or more than two capacitor plates. The leakage sensors and switching devices are employed to electrically disconnect any capacitor module of the capacitor array that becomes leaky, thereby protecting the capacitor array from excessive electrical leakage.

    24.
    发明专利
    未知

    公开(公告)号：DE69303764T2

    公开(公告)日：1997-02-06

    申请号：DE69303764

    申请日：1993-04-22

    Applicant: IBM

    Inventor： BUTI TAQI NASSER ,  HSU LOUIS LU-CHEN ,  JOST MARK EDWIN ,  OGURA SEIKI NMN OGURA SEIKI NM ,  SCHULZ RONALD NORMAN

    IPC: H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8249 ,  H01L29/73 ,  H01L27/06 ,  H01L27/08 ,  H01L27/12 ,  H01L29/732 ,  H01L29/786 ,  H01L21/82 ,  H01L21/304

    Abstract: A SOI BiCMOS integrated circuit has CMOS devices formed in a thin epitaxial layer of 1000 ANGSTROM and bipolar devices formed in a thick epitaxial layer of 1 mu m, the two thicknesses being formed by a process in which a set of oxide islands are formed on a first wafer; an epitaxial layer is grown from bipolar silicon regions up and over the islands in a step that forms the bottom portion of the bipolar regions; the first wafer is inverted and oxide- bonded to a second wafer with the newly grown epitaxial layer below the islands so that the new top surface has a high quality epitaxial layer; excess silicon is removed from the new surface and the surface is polished to a thickness of 1000 ANGSTROM over the islands by use of a nitride polish stop layer, leaving a thick layer of epitaxial silicon of 1 mu m in the bipolar regions and a 1000 ANGSTROM thick layer of epitaxial silicon in the CMOS regions.

    SEMICONDUCTOR DEVICE AND WAFER STRUCTURE HAVING A PLANAR BURIED INTERCONNECT BY WAFER BONDING
    25.
    发明专利
    SEMICONDUCTOR DEVICE AND WAFER STRUCTURE HAVING A PLANAR BURIED INTERCONNECT BY WAFER BONDING 未知

    公开(公告)号：CA2105039C

    公开(公告)日：1996-10-29

    申请号：CA2105039

    申请日：1993-08-27

    Applicant: IBM

    Inventor： BUTI TAQI NASSER ,  HSU LOUIS LU-CHEN ,  JOSHI RAJIV VASANT ,  SHEPARD JOSEPH FRANCIS

    IPC: H01L21/3205 ,  H01L21/74 ,  H01L21/762 ,  H01L21/768 ,  H01L21/822 ,  H01L21/98 ,  H01L23/522 ,  H01L27/04 ,  H01L21/44 ,  H01L21/441 ,  H01L21/48

    Abstract: A wafer structure suitable for the formation of semiconductor devices thereon and having a buried interconnect structure for interconnection of desired ones of the semiconductor devices according to a predetermined interconnection pattern and a method of making the same is disclosed. The wafer structure comprises a primary substrate having a first thickness appropriate for the formation of the desired semiconductor devices. The primary substrate further comprises a) conductive interconnection pads of a second thickness formed on a bottom surface of the primary substrate according to the predetermined interconnection pattern, b) first isolation pads of a third thickness formed on the bottom surface of the primary substrate between the conductive interconnection pads, and c) interconnection pad caps of a fourth thickness formed upon the surface of the interconnection pads opposite from the primary substrate, wherein the interconnection pad caps comprise a material suitable for wafer bonding, and further wherein the total thickness of the second thickness and the fourth thickness equals the third thickness. The structure further comprises a secondary substrate having an oxide layer thereon bonded to the interconnection pad caps and the first isolation pads of the primary wafer.

    Electronic structure having in-situ resistors
    28.
    发明专利
    Electronic structure having in-situ resistors 未知

    公开(公告)号：AU9209001A

    公开(公告)日：2002-04-22

    申请号：AU9209001

    申请日：2001-10-05

    Applicant: IBM

    Inventor： CLEVENGER LAWRENCE ,  HSU LOUIS LU-CHEN ,  WONG KWONG HON

    IPC: H01L21/02 ,  H01L27/06

    Abstract: An electronic structure that has in-situ formed unit resistors and a method for fabricating such structure are disclosed. The electronic structure that has in-situ formed unit resistors consists of a first plurality of conductive elements formed in an insulating material layer, a plurality of electrically resistive vias formed on top and in electrical communication with at least one of the first plurality of conductive elements, and a second plurality of conductive elements formed on top of and in electrical communication with at least one of the plurality of electrically resistive vias. The present invention novel structure may further be formed in a multi-level configuration such that multi-level resistors may be connected in-series to provide larger resistance values. The present invention novel structure may further be combined with a capacitor network to form desirable RC circuits.

    30.
    发明专利
    未知

    公开(公告)号：DE69303764D1

    公开(公告)日：1996-08-29

    申请号：DE69303764

    申请日：1993-04-22

    Applicant: IBM

    Inventor： BUTI TAQI NASSER ,  HSU LOUIS LU-CHEN ,  JOST MARK EDWIN ,  OGURA SEIKI NMN OGURA SEIKI NM ,  SCHULZ RONALD NORMAN

    IPC: H01L21/331 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8249 ,  H01L29/73 ,  H01L27/06 ,  H01L27/08 ,  H01L27/12 ,  H01L29/732 ,  H01L29/786 ,  H01L21/82 ,  H01L21/304

    Abstract: A SOI BiCMOS integrated circuit has CMOS devices formed in a thin epitaxial layer of 1000 ANGSTROM and bipolar devices formed in a thick epitaxial layer of 1 mu m, the two thicknesses being formed by a process in which a set of oxide islands are formed on a first wafer; an epitaxial layer is grown from bipolar silicon regions up and over the islands in a step that forms the bottom portion of the bipolar regions; the first wafer is inverted and oxide- bonded to a second wafer with the newly grown epitaxial layer below the islands so that the new top surface has a high quality epitaxial layer; excess silicon is removed from the new surface and the surface is polished to a thickness of 1000 ANGSTROM over the islands by use of a nitride polish stop layer, leaving a thick layer of epitaxial silicon of 1 mu m in the bipolar regions and a 1000 ANGSTROM thick layer of epitaxial silicon in the CMOS regions.

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