公开(公告)号：DE69636861D1

公开(公告)日：2007-03-15

申请号：DE69636861

申请日：1996-08-29

Applicant: IBM

Inventor： KAHLE JAMES A ,  LOPER ALBERT J ,  MALLICK SOUMMYA ,  OGDEN AUBREY D

IPC: G06F9/312 ,  G06F9/38 ,  G06F12/00

Abstract: A load multiple instruction may be executed in a superscaler microprocessor by dispatching a load multiple instruction to a load/store unit, wherein the load/store unit begins execution of a dispatched load multiple instruction, and wherein the load multiple instruction loads data from memory into a plurality of registers. A table is maintained that lists each register of the plurality of registers and that indicates when data has been loaded into each register by the executing load multiple instruction. An instruction is executed that is dependent upon source operand data loaded by the load multiple instruction, prior to the load multiple instruction completing its execution, when the table indicates the source operand data has been loaded into the source register. Also, a store multiple instruction may be executed by dispatching a store multiple instruction to the load/store unit, whereupon the load/store unit begins executing the store multiple instruction, wherein the load/store instruction stores data from a plurality of registers to memory. A fixed point instruction is executed that is dependent upon data being stored by the store multiple instruction prior to the store multiple instruction completing its execution, but the executing fixed point instruction is prohibited from writing to a register of the plurality of registers prior to the store multiple instruction completing.

公开(公告)号：HK1070719A1

公开(公告)日：2005-06-24

申请号：HK05103951

申请日：2005-05-11

Applicant: IBM

Inventor： DAY MICHAEL N ,  JOHNS CHARLES R ,  KAHLE JAMES A ,  LIU PEICHUM P ,  TRUONG THUONG QUANG

IPC: G06F20060101 ,  G06F12/08 ,  G06F9/46 ,  G06F13/14 ,  G06F13/28

Abstract: The present invention provides for atomic update primitives in an asymmetric single-chip heterogeneous multiprocessor computer system having a shared memory with DMA transfers. At least one lock line command is generated from a set comprising a get lock line command with reservation, a put lock line conditional command, and a put lock line unconditional command.

公开(公告)号：DE69322244D1

公开(公告)日：1999-01-07

申请号：DE69322244

申请日：1993-12-27

Applicant: IBM

Inventor： KAHLE JAMES A ,  MUHICH JOHN S ,  OEHLER RICHARD R ,  SILHA EDWARD J

IPC: G06F15/16 ,  G06F12/10 ,  G06F15/177 ,  G06F12/12

Abstract: A method and system for increasing memory concurrency in a multiprocessor computer system where each processor includs an associated Translation Lookaside Buffer (TLB) for translating effective addresses into real memory addresses. Multiple page table entries are provided within a page table within the system memory which each include multiple individually accessible fields. A reference bit is provided within a first individually accessible field within each page table entry and it is utilized to indicate if an associated system memory location has been accessed for a read or write operation. A change bit is provided within a second individually accessible field within each page table entry and it is utilized to indicate if an associated system memory location has been modified by a write operation. By storing the reference bit and change bit in separate individually accessible fields the reference bit and change bit may be concurrently updated by multiple processors.

公开(公告)号：DE69322064D1

公开(公告)日：1998-12-17

申请号：DE69322064

申请日：1993-12-27

Applicant: IBM

Inventor： KAHLE JAMES A ,  KAU CHIN-CHENG ,  LEVITAN DAVID S ,  OGDEN AUBREY D ,  POURSEPANJ ALI A ,  KANG-GUO TU PAUL ,  WALDECKER DONALD E

IPC: G06F9/38

Abstract: A method and system for permitting single cycle instruction dispatch in a superscalar processor system which dispatches multiple instructions simultaneously to a group of execution units (24) for execution and placement of results thereof within specified general purpose registers (44, 46). Each instruction generally includes at least one source operand and one destination operand. A plurality of intermediate storage buffers (40, 42) are provided and each time an instruction is dispatched to an available execution unit (24), a particular one of the intermediate storage buffers (40, 42) is assigned to any destination operand within the dispatched instruction, permitting the instruction to be dispatched within a single cycle by eliminating any requirement for determining and selecting the specified general purpose register (44, 46) or a designated alternate general purpose register.

公开(公告)号：PH30201A

公开(公告)日：1997-02-05

申请号：PH39687

申请日：1989-12-13

Applicant: IBM

Inventor： GROHOSKI GREGORY F ,  KAHLE JAMES A ,  NGUYENPHU MYHONG ,  RAY DAVID S

IPC: G06F9/38 ,  G06F15/16 ,  G06F9/48 ,  G06F1/00

Abstract: A data processing system including an instruction storage buffer for storing a sequence of instructions requiring an operation by at least two processors. The two processors are provided that execute instructions from the instruction storage buffer. An instruction dispatch circuit is provided that dispatches the instructions to the processors. At least one processor includes the capability to execute dispatched instructions before the execution of a preceding instruction in the instruction sequence by another processor. Also, at least one processor includes the capability to delay execution of an interruptable instruction until the instruction can be executed in its appropriate sequential order in the sequence. Also, upon the occurrence of the interrupt, the processors include the capability to purge the instruction storage buffer in order that the interrupt software instructions may be stored for execution.

公开(公告)号：CA2107056A1

公开(公告)日：1994-07-09

申请号：CA2107056

申请日：1993-09-27

Applicant: IBM

Inventor： KAHLE JAMES A ,  MUHICH JOHN S ,  OEHLER RICHARD R ,  SILHA EDWARD J

IPC: G06F15/16 ,  G06F12/10 ,  G06F15/177

Abstract: A method and system for increasing memory concurrency in a multiprocessor computer system where each processor includs an associated Translation Lookaside Buffer (TLB) for translating effective addresses into real memory addresses. Multiple page table entries are provided within a page table within the system memory which each include multiple individually accessible fields. A reference bit is provided within a first individually accessible field within each page table entry and it is utilized to indicate if an associated system memory location has been accessed for a read or write operation. A change bit is provided within a second individually accessible field within each page table entry and it is utilized to indicate if an associated system memory location has been modified by a write operation. By storing the reference bit and change bit in separate individually accessible fields the reference bit and change bit may be concurrently updated by multiple processors.