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    Producing horizontal insulation layer on conducting material in trench, deposits insulant layer over trench- and sidewall structures, followed by controlled removal
    23.
    发明专利
    Producing horizontal insulation layer on conducting material in trench, deposits insulant layer over trench- and sidewall structures, followed by controlled removal 未知

    公开(公告)号：DE10212610C1

    公开(公告)日：2003-11-06

    申请号：DE10212610

    申请日：2002-03-21

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： POPP MARTIN

    IPC: H01L21/762 ,  H01L21/763 ,  H01L21/8242

    Abstract: The trench is prepared in the surface of a semiconductor substrate (10). A layer of silicon nitride or oxide (12) is formed on it and has a surface (16). The upper region of the trench has partially-exposed side walls (18) with an oxide collar (14) on them. The lower region is filled with a conductive material (13) up to a depth below the surface. An insulant is deposited on the substrate, forming an insulating layer (14) in the trench, with a horizontal layer thickness (22) above the conducting layer. The first layer is thinner than the second (22). Insulant is deposited such that the trench is filled to a second depth (21) below the surface (16) of the silicon nitride- or -oxide layer (12). The insulant is removed from this layer (12) on the substrate. A first isotropic etching of the insulant (14') takes material from the surface, the depth exceeding the horizontal layer thickness (23) and being less than the vertical layer thickness (22). This removes insulant on the sidewalls of the trench. A horizontal insulating layer (14') with a layer thickness remains on the conducting material.

    25.
    发明专利
    未知

    公开(公告)号：DE10131675A1

    公开(公告)日：2003-01-16

    申请号：DE10131675

    申请日：2001-06-29

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： LINDOLF JUERGEN ,  POPP MARTIN ,  SELL BERNHARD

    IPC: G01R27/26 ,  G11C29/50 ,  G11C11/4076

    Abstract: A ring oscillator has a multiplicity of inverters. An interconnect is connected between two of the inverters, and a storage capacitor to be measured, with its associated lead resistor, is coupled to the interconnect either via an interconnect or a transistor can selectively coupled and decouple the capacitor and the lead resistance. A measuring device is connected up to the ring oscillator and is used to determine a value for the oscillation frequency of the ring oscillator on the basis of which a value for the time constant of the storage capacitor can be determined.

    26.
    发明专利
    未知

    公开(公告)号：DE102005047058A1

    公开(公告)日：2007-04-12

    申请号：DE102005047058

    申请日：2005-09-30

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： SCHLOESSER TILL ,  WEIS ROLF ,  MOLL HANS-PETER ,  POPP MARTIN ,  STRASSER MARC ,  LUYKEN HANNES

    IPC: H01L21/336 ,  H01L29/78

    Abstract: In a method for producing a trench transistor, a substrate of a first conduction type is provided and a trench in the substrate and a gate dielectric in the trench are formed. A first conductive filling in the trench as a gate electrode on the gate dielectric and first source and drain regions are formed. An etched-back first conductive filling is produced by etching back the first conductive filling down to a depth below the first source and drain regions and second source and drain regions are formed. The second source and drain regions adjoin the first source and drain regions and extend to a depth at least as far as the etched-back first conductive filling. An insulation spacer above the etched-back first conductive filling is formed in the trench and a second conductive filling is provided in the trench as an upper part of the gate electrode.

    27.
    发明专利
    未知

    公开(公告)号：DE10314595B4

    公开(公告)日：2006-05-04

    申请号：DE10314595

    申请日：2003-03-31

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： POPP MARTIN ,  HEINECK LARS

    IPC: H01L21/8238 ,  H01L21/8234 ,  H01L21/8239 ,  H01L21/8242 ,  H01L27/108

    Abstract: Production of transistors (3,3') of different conductivity type in the first section of a surface of a semiconductor substrate (10) comprises forming a gate electrode layer (12) of first conductivity type doping on the substrate, producing gate structures (5) assigned to the transistors, forming a spacer structure and a covering structure to encapsulate the gate structures, using the encapsulated gate structures as masks and/or conducting structures for the self-adjusting contact of the transistors in a first section of the substrate, applying a protective layer (14) in the region of the first section, opening encapsulated gate structures by selectively removing the covering structures so that a part of the gate electrodes (7) of the gate structures is exposed, doping the gate electrode and the assigned source/drain regions (6,6') of the transistors with a dopant of second conductivity type.

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