公开(公告)号：DE102012111831A1

公开(公告)日：2013-06-13

申请号：DE102012111831

申请日：2012-12-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DETZEL THOMAS ,  GROSS JOHANN ,  ILLING ROBERT ,  KRUG MAXIMILIAN ,  LANZERSTORFER SVEN GUSTAV ,  NELHIEBEL MICHAEL ,  ROBL WERNER ,  ROGALLI MICHAEL ,  WOEHLERT STEFAN

IPC: H01L23/532 ,  H01L21/768 ,  H01L27/04

Abstract: Eine integrierte Schaltung umfasst ein Basiselement (1) und ein Kupferelement (2) über dem Basiselement (1), wobei das Kupferelement (2) eine Dicke von wenigstens 5 µm hat und ein Verhältnis einer mittleren Korngröße zur Dicke kleiner als 0,7 ist.

公开(公告)号：DE10305618B4

公开(公告)日：2007-10-11

申请号：DE10305618

申请日：2003-02-11

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOETSCHKES UDO ,  MOELLER HOLGER ,  ROGALLI MICHAEL ,  REB ALEXANDER ,  TRINOWITZ REINER

IPC: G03F7/20 ,  G03F1/00 ,  G03F1/08 ,  G03F7/00 ,  G03F7/09 ,  G03F7/095

公开(公告)号：DE10211544C1

公开(公告)日：2003-11-27

申请号：DE10211544

申请日：2002-03-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNEEGANS MANFRED ,  JAEGER WOLFGANG ,  ROGALLI MICHAEL

IPC: H01L21/288 ,  H01L21/8242 ,  H01G4/33

Abstract: A method for producing metal layers on surfaces of semiconductor substrates includes the step of providing a semiconductor substrate having a surface. In this case, a precursor compound of a metal to be deposited is condensed out on the semiconductor surface and subsequently decomposed thermally. The method makes it possible to fill trenches with a high aspect ratio, it being possible to effectively suppress the formation of voids.

公开(公告)号：DE10154966A1

公开(公告)日：2003-05-22

申请号：DE10154966

申请日：2001-10-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROGALLI MICHAEL ,  REB ALEXANDER ,  VOELKEL LARS ,  STEGEMANN MAIK

IPC: G03F7/40 ,  H01L21/311 ,  H01L21/3213 ,  G03F7/36 ,  G03F7/20 ,  H01L21/3065

Abstract: The invention relates to a process for the production of a semiconductor apparatus, in which an etch step is carried out after an exposure step using light having a wavelength of 193 nm and a development step, the etch gas used containing an added reactive monomer. As a result, polymerization of the surface and hence sidewall passivation of the photoresist used are achieved.

公开(公告)号：DE10053467A1

公开(公告)日：2002-05-16

申请号：DE10053467

申请日：2000-10-27

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LAHNOR PETER ,  WEGE STEPHAN ,  ROGALLI MICHAEL

IPC: H01L21/321 ,  H01L21/768 ,  H01L21/283

Abstract: The method involves producing a substrate (10) with insulating layer (15), providing a hard mask layer (20), structuring an opening in the mask layer according to the contact to be formed, optionally providing a spacer layer (40) in the opening, etching a contact hole using the opening, applying a liner coating (50), applying a contact material (60) so as to fill the contact hole and chemically-mechanically polishing the resulting structure.

公开(公告)号：DE19961103C2

公开(公告)日：2002-03-14

申请号：DE19961103

申请日：1999-12-17

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ROGALLI MICHAEL ,  KIRCHHOFF MARKUS ,  WEGE STEPHAN

IPC: H05K1/03 ,  H01L21/283 ,  H01L21/312 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/314

Abstract: Electric wiring of an IC comprises: a base body (1); a conductive layer (2) patterned into two conductor tracks (3,4) with a trench (5) between; and a dielectric layer (9) on the conductive layer, at least partially filling the trench. The dielectric layer is at least one polymer selected from polybenzoxazole, polynorbornene and derivatives. Independent claims are also included for: (a) electrical wiring, in which the polymer material is selected from fluorinated derivatives of polybenzoxazole, polynorbornene, polyimide and perylene polymer; and (b) a process to produce the electrical wiring, by: forming the conductive layer (2) on a base body (1), patterning and spin coating at least one dielectric polymer layer onto the conductive layer so the trench (5) is at least partially filled.