公开(公告)号：DE59911513D1

公开(公告)日：2005-03-03

申请号：DE59911513

申请日：1999-05-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAMBERGER FLORIAN ,  SCHNEIDER HELMUT

IPC: H01L21/60 ,  G01R31/02 ,  G01R31/316 ,  H01L21/66 ,  H01L23/485

Abstract: A bonding pad test configuration for establishing whether or not a semiconductor chip is bonded. The test configuration has a circuit that evaluates a state of a bond between a bonding wire and the bonding pad and is able to activate and deactivate operating and test modes depending on the bond state established. To this end, the bonding pad is divided into at least two parts, so that the circuit produced in the semiconductor chip itself can use signals derived from the parts of the bonding pad to establish whether or not the bonding wire is in contact with the parts.

公开(公告)号：DE10318604A1

公开(公告)日：2004-11-25

申请号：DE10318604

申请日：2003-04-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ENDERS GERHARD ,  FISCHER BJOERN ,  SCHNEIDER HELMUT ,  VOIGT PETER

IPC: H01L29/06 ,  H01L29/10 ,  H01L29/78

Abstract: The device has a semiconducting substrate (402) with a source region, a drain region and a channel region, whereby the source and drain regions are connected to source (404) and drain (406) electrodes, the channel region has first and second constriction regions connected in parallel with respect to the source and drain electrodes and a gate electrode (408) arranged above the first and second constriction channel regions.

公开(公告)号：DE10107182B4

公开(公告)日：2004-10-14

申请号：DE10107182

申请日：2001-02-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KEYSERLINGK ALBERT GRAF VON ,  SCHAFFROTH THILO ,  SCHNEIDER HELMUT

IPC: G11C11/408 ,  G11C8/08 ,  G11C11/407

公开(公告)号：DE10217710C1

公开(公告)日：2003-11-20

申请号：DE10217710

申请日：2002-04-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KEYSERLINGK ALBERT ,  SCHNEIDER HELMUT ,  PFEIFFER JOHANN

IPC: G06F11/16 ,  G11C17/16 ,  G11C17/18 ,  G11C29/00

Abstract: A semiconductor circuit has at least one generator fuse for setting a supply voltage and at least one redundancy fuse for activating a redundancy element. A first read-out device is provided for reading out the generator fuse and a second read-out device reads out the redundancy fuse. The first read-out device is configured to read out the generator fuse at a first instant, and the second read-out device is configured to read out the redundancy fuse at a second instant.

公开(公告)号：DE10219105A1

公开(公告)日：2003-11-13

申请号：DE10219105

申请日：2002-04-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNEIDER HELMUT ,  BENZINGER HERBERT

IPC: H01L21/762 ,  H01L21/763 ,  H01L21/8242 ,  H01L27/108

Abstract: Integrated memory cell (1) comprises two storage cells (11, 21) and a trench insulation (15) for electrically insulating the storage cells and having an electrically conducting structure (16) and an electrically insulating casing (17). The casing electrically insulates the conducting structure from the storage cells. An Independent claim is also included for a process for the production of the integrated memory cell.

公开(公告)号：DE10135814C2

公开(公告)日：2003-09-18

申请号：DE10135814

申请日：2001-07-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNEIDER HELMUT ,  SCHRAMM ACHIM

IPC: G11C7/12 ,  G11C8/08 ,  G11C11/408 ,  G11C11/4094 ,  G11C11/407

Abstract: The application of a nonactive level to a word line in a semiconductor memory is controlled by a precharge control. In order to initiate the precharge operation, a pair of reference bit lines are provided to which initially different potentials can be fed, which are subsequently amplified by a reference sense amplifier. The potential of one of the reference bit lines is amplified in a differential amplifier in order thereupon to cause a control device to initiate the precharge operation.

公开(公告)号：DE10135814A1

公开(公告)日：2003-02-13

申请号：DE10135814

申请日：2001-07-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNEIDER HELMUT ,  SCHRAMM ACHIM

IPC: G11C7/12 ,  G11C8/08 ,  G11C11/408 ,  G11C11/4094

Abstract: The application of a nonactive level to a word line in a semiconductor memory is controlled by a precharge control. In order to initiate the precharge operation, a pair of reference bit lines are provided to which initially different potentials can be fed, which are subsequently amplified by a reference sense amplifier. The potential of one of the reference bit lines is amplified in a differential amplifier in order thereupon to cause a control device to initiate the precharge operation.

公开(公告)号：DE10124753A1

公开(公告)日：2002-12-12

申请号：DE10124753

申请日：2001-05-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： PFEFFERL PETER ,  SAVIGNAC DOMINIQUE ,  SCHNEIDER HELMUT ,  CHRYSOSTOMIDES ATHANASIA ,  KLING SABINE

IPC: G11C7/06

Abstract: The method involves applying a binary memory cell signal(s) to a bit line pair(s), connecting the signal to a detection amplifier(s) depending on a cell field control signal(s), connecting a binary output signal to a local data line pair as a binary intermediate signal depending on a column control signal, connecting the intermediate signal to a main data line pair(s) depending on a line control signal and outputting a binary output signal. The method involves applying at least one binary memory cell signal to at least one bit line pair (201t,201b), connecting the signal to at least one detection amplifier (202-0 to 202-7) depending on at least one cell field control signal, connecting a binary output signal to a local data line pair as a binary intermediate signal depending on a column control signal, connecting the intermediate signal to at least one main data line pair depending on a line control signal and outputting a binary output signal

公开(公告)号：DE10117614A1

公开(公告)日：2002-10-17

申请号：DE10117614

申请日：2001-04-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN ,  SCHNEIDER HELMUT

IPC: G11C11/401 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407

Abstract: A method for operating a semiconductor memory at a data transmission rate which is twice as fast. According to the invention, data read access and data write access is divided up into two memories. A first memory bank is operated at one speed which is offset by a factor of 0.5 in relation to the operating speed of the second memory bank and the data partial flows are combined at the output of the two memory banks to form a data flow at a frequency which is multiplied by two.

公开(公告)号：DE10114443A1

公开(公告)日：2002-09-26

申请号：DE10114443

申请日：2001-03-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  SCHAMBERGER FLORIAN ,  SCHNEIDER HELMUT

IPC: G11C7/10 ,  G11C8/04 ,  G11C7/00

Abstract: The method involves writing a data item into a memory cell selected by an address decoder, whereby the address is fed to the address decoder and the data item to the memory. The address is fed in earlier than the data item and is temporarily stored, then passed to the address decoder following a delay. The address and data item are almost simultaneously fed to the address decoder or amplifier circuit. AN Independent claim is also included for the following: a memory arrangement.