公开(公告)号：DE112018004957T5

公开(公告)日：2020-07-16

申请号：DE112018004957

申请日：2018-10-25

Applicant: MICROCHIP TECH INC

Inventor： YUENYONGSGOOL YONG ,  BOWLING STEPHEN ,  VAN EEDEN COBUS ,  WOJEWODA IGOR ,  RAJ NAVEEN

IPC: G06F13/28

Abstract: Eine Speicherverwaltungsschaltung beinhaltet einen DMA-Kanal (Direct Memory Access). Der DMA-Kanal beinhaltet eine Logik, die konfiguriert ist, um einen Puffer von Daten zu empfangen, die unter Verwendung von DMA geschrieben werden sollen. Der DMA-Kanal beinhaltet weiterhin eine Logik zum Durchführen einer Bitmanipulation in Echtzeit während eines DMA-Schreibzyklus des ersten Puffers von Daten.

公开(公告)号：AT534077T

公开(公告)日：2011-12-15

申请号：AT06735222

申请日：2006-02-16

Applicant: MICROCHIP TECH INC

Inventor： MASGRAS CRISTIAN ,  PYSKA MICHAEL ,  BOLES EDWARD ,  TRIECE JOSEPH ,  WOJEWODA IGOR ,  CHEN MEI-LING

IPC: G06F11/27 ,  G11C29/46

Abstract: A special mode key match comparison module has N-storage elements and a special mode key match comparator. The N-storage elements accumulate a serial data stream, and then determine whether a digital device should operate in a normal user mode, in a public programming mode, or in a particular private test mode. To reduce the possibility of accidentally decoding a false test or programming mode, the data stream has a sufficiently large number of N-bits to substantially reduce the probability of a false decode. To further reduce the possibility of accidentally decoding a programming or test mode, the special mode key match comparison module may be reset if less or more than N-clocks are detected during the accumulation of the N-bit serial data stream. The special mode key match data patterns may represent a normal user mode, a public programming mode, and particular private manufacturer test modes.

公开(公告)号：DE69808020D1

公开(公告)日：2002-10-24

申请号：DE69808020

申请日：1998-10-14

Applicant: MICROCHIP TECH INC

Inventor： DRAKE RODNEY J ,  TRIECE JOSEPH W ,  YACH RANDY L ,  BOLES BRIAN ,  WOJEWODA IGOR ,  JOHANSEN DARREL

IPC: G06F9/35

Abstract: A data pointer for generating an indirect addressing mode address within a single cycle for a selected one of a plurality of multiple indirect addressing modes. The data pointer is used with a processor architecture scheme which allows for encoding of multiple addressing modes. A data pointer register is coupled to the processor architecture scheme for storing a current address of an operand to be used in a simple indirect addressing mode. An incrementer is coupled to the data pointer register for incrementing the current address of an operand to be used in a simple indirect data addressing mode by a set number thereby generating an address of an operand to be used in an indirect addressing mode with auto preincrement. An adder is coupled to the data pointer register for combining the current address of an operand to be used in a simple indirect data addressing mode with an offset number thereby generating an address of an operand to be used in an indirect addressing mode with offset. A multiplexer circuit is coupled to an output of the data pointer register, to an output of the incrementer, and to an output of the adder for selecting a desired indirect addressing mode address.

公开(公告)号：AT204393T

公开(公告)日：2001-09-15

申请号：AT98119390

申请日：1998-10-14

Applicant: MICROCHIP TECH INC

Inventor： DRAKE RODNEY J ,  CHIAO JENNIFER ,  YACH RANDY L ,  WOJEWODA IGOR ,  TRIECE JOSEPH W ,  ALLEN STEVE

IPC: G06F9/32 ,  G06F9/34 ,  G06F9/38

Abstract: A system for allowing a two word instruction to be executed in a single cycle thereby allowing a processor system to increase memory space without reducing performance. A first address bus is coupled to the linearized program memory for sending addresses of instructions to be fetched to a linearized program memory. A pointer is coupled to the first address bus for storing an address location of a current instruction in the linearized program memory to be fetched and for placing the address location of the current instruction to be fetched on the first address bus. A second address bus is provided and has one end coupled to the output of the program memory and a second end coupled to the first address bus. The second address bus is used for placing an address of an operand of a second word of the two word instruction onto the first address bus after an address of an operand of a first word of the two word instruction has been placed on the first address bus. This allows the addresses of the first word and the second word to be combined to provide the full address value of the two word instruction in a single cycle.

公开(公告)号：WO2014149583A8

公开(公告)日：2015-05-28

申请号：PCT/US2014019737

申请日：2014-03-01

Applicant: MICROCHIP TECH INC

Inventor： SIMMONS MICHAEL ,  WOJEWODA IGOR ,  SAMUEL ROSHAN

IPC: G06F9/445 ,  G06F9/44

CPC classification number: G06F1/24 ,  G06F8/67 ,  G06F9/4401 ,  G06F9/4406 ,  G06F9/4411 ,  G06F9/44505

Abstract: A method for hot swapping an operating system kernel in a system, wherein the system comprises a central processing unit, one or more system components and a program memory including an old kernel and a new kernel, the method comprising: - configuring, by the old kernel, the system to boot from the new kernel by branching into a suitable entry point in the new kernel; - identifying, by the new kernel, one or more system components which require a reinitialization or reset; - further executing the new kernel in order to reinitialize or reset the one or more system components.

Abstract translation: 一种用于热交换系统中的操作系统内核的方法，其中所述系统包括中央处理单元，一个或多个系统组件以及包括旧内核和新内核的程序存储器，所述方法包括： - 由旧的 内核，系统通过分支到新内核中的合适入口点从新内核引导; - 由新内核识别需要重新初始化或重置的一个或多个系统组件; - 进一步执行新内核以重新初始化或重置一个或多个系统组件。

公开(公告)号：WO2007143494A3

公开(公告)日：2008-03-13

申请号：PCT/US2007070066

申请日：2007-05-31

Applicant: MICROCHIP TECH INC ,  WOJEWODA IGOR ,  BOLES BRIAN ,  BRADLEY STEVE ,  KAVAIYA GAURANG

Inventor： WOJEWODA IGOR ,  BOLES BRIAN ,  BRADLEY STEVE ,  KAVAIYA GAURANG

IPC: H03K19/0175

CPC classification number: H03K19/17764 ,  H03K19/1732 ,  H03K19/17744

Abstract: Peripheral functions of an integrated circuit device may be pooled and dynamically mapped to available external input-output connections of the integrated circuit device by using a set of configuration registers. To provide system robustness, the configuration registers may implement various levels of write protection, error correction and monitoring circuitry. One or more peripheral output functions may be mapped to one or more external output connections. Not more than one output function may be active at the same time on the same output connection. Outputs and inputs may be mapped to the same external input- output connection with or without the output being controllable for placement into an inactive state, e.g., high impedance or open collector. When the input is required to receive external data over the external input-output connection, the output may be placed into the inactive state.

Abstract translation: 通过使用一组配置寄存器，集成电路设备的外围功能可以被集合并且动态地映射到集成电路设备的可用的外部输入 - 输出连接。 为了提供系统的鲁棒性，配置寄存器可以实现各种级别的写保护，纠错和监视电路。 一个或多个外围输出功能可以映射到一个或多个外部输出连接。 在同一输出连接上，同一输出功能可能同时处于活动状态。 输出和输入可以被映射到相同的外部输入 - 输出连接，具有或不具有可控制的输出以放置到非活动状态，例如高阻抗或开路集电极。 当输入需要通过外部输入 - 输出连接接收外部数据时，输出可能被置于非活动状态。

公开(公告)号：WO2005119468A2

公开(公告)日：2005-12-15

申请号：PCT/US2005018649

申请日：2005-05-26

Applicant: MICROCHIP TECH INC ,  WOJEWODA IGOR ,  FOSLER ROSS ,  ROJVANIT RAWIN

Inventor： WOJEWODA IGOR ,  FOSLER ROSS ,  ROJVANIT RAWIN

IPC: G06F13/38

CPC classification number: G06F13/38

Abstract: A digital device having selectable modes for USB communications buffer management in a USB interface of the digital device. These modes may comprise (1) no ping-pong buffer support, (2) ping-pong buffer support for some endpoints, e.g., support for OUT endpoint 0 only, and (3) ping-pong buffer support for all endpoints. In the no ping­pong buffer support mode, no hardware is required for automatic ping-pong buffer management. The Buffer Descriptor Tables may comprise a maximum of 128 memory locations, e.g., 16 IN endpoints and 16 OUT endpoints, each with at least one buffer descriptor, and each comprising four (4) memory locations. In the ping-pong buffer support for OUT endpoint 0 only mode, the buffer descriptor Tables may comprise a maximum of 132 memory locations, e.g., 16 OUT endpoints with an EVEN and an ODD endpoint 0, 16 IN endpoints, each with at least one descriptor, e.g., memory locations. This mode assures that endpoint 0 setup transfers may be serviced without delay while only requiring a minimal number of memory locations for the remainder of the buffer descriptors. In the ping-pong buffer support for all endpoints mode, automatic ping-pong buffer management may be provided for all endpoints. The Buffer Descriptor Tables may comprise a maximum of 256 memory locations, e.g., 16 IN endpoints and 16 OUT endpoints, an EVEN and ODD set for each, each with one descriptor, e.g., four (4) memory locations. This mode assures that all endpoint transfers may be serviced substantially without delay.

Abstract translation: 一种数字设备，其具有用于在数字设备的USB接口中进行USB通信缓冲器管理的可选模式。 这些模式可以包括（1）无乒乓缓冲器支持，（2）对某些端点的乒乓缓冲器支持，例如仅支持OUT端点0，以及（3）对所有端点的乒乓缓冲器支持。 在无乒乓缓冲支持模式下，无需硬件自动乒乓缓冲区管理。 缓冲器描述符表可以包括最多128个存储器位置，例如16个IN端点和16个OUT端点，每个具有至少一个缓冲器描述符，并且每个包括四（4）个存储单元。 在乒乓缓冲区支持OUT端点0唯一模式下，缓冲区描述符表可以包含最多132个存储器位置，例如16个OUT端点，其中EVEN和ODD端点为0,16 IN端点，每个端点至少有一个 描述符，例如内存位置。 该模式确保端点0建立传输可以无延迟地被服务，而仅需要缓冲器描述符的其余部分的最小数量的存储器位置。 在所有端点模式的乒乓缓冲区支持中，可以为所有端点提供自动乒乓缓冲区管理。 缓冲器描述符表可以包括最多256个存储器位置，例如16个IN端点和16个OUT端点，为每个存储单元设置一个EVEN和ODD，每个具有一个描述符，例如四（4）个存储器位置。 该模式确保所有端点传输可以在没有延迟的情况下得到实质的维护。

公开(公告)号：WO2016149086A3

公开(公告)日：2016-11-03

申请号：PCT/US2016021977

申请日：2016-03-11

Applicant: MICROCHIP TECH INC

Inventor： KRIS BRYAN ,  WOJEWODA IGOR ,  CATHERWOOD MIKE ,  FALL BRIAN ,  TOLLEFSON JASON ,  PEPPING JIM ,  MICKEY DAVE ,  SPOHRER THOMAS ,  DUMAIS ALEX ,  WILKIE CALUM ,  SHEARD VINCENT

IPC: G06F15/167 ,  G06F1/22 ,  G06F13/38

CPC classification number: G06F13/4282 ,  G06F1/22 ,  G06F13/1673 ,  G06F13/364 ,  G06F13/385 ,  G06F15/167 ,  Y02D10/14 ,  Y02D10/151

Abstract: A microcontroller device has a housing with a plurality of external pins. a first microcontroller with a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, and a second microcontroller with a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, wherein first and second microcontroller communicate only via a dedicated interface.

Abstract translation: 微控制器装置具有带有多个外部引脚的外壳。 具有第一中央处理单元（CPU）的第一微控制器，与第一CPU耦合的第一系统总线，与第一系统总线耦合的第一存储器以及与第一系统总线耦合的第一多个外围设备，以及第二微控制器 与第二中央处理单元（CPU），与第二CPU耦合的第二系统总线，与第二系统总线耦合的第二存储器以及与第二系统总线耦合的第二多个外围设备，其中第一与第二微控制器仅通信 通过专用接口。

公开(公告)号：WO2016149078A3

公开(公告)日：2016-11-03

申请号：PCT/US2016021962

申请日：2016-03-11

Applicant: MICROCHIP TECH INC

Inventor： KRIS BRYAN ,  WOJEWODA IGOR ,  CATHERWOOD MIKE ,  FALL BRIAN ,  TOLLEFSON JASON ,  WILKIE CALUM ,  MICKEY DAVE ,  SPOHRER THOMAS ,  DUMAIS ALEX

IPC: G06F15/78 ,  G06F13/38

CPC classification number: G06F13/4282 ,  G06F13/1673 ,  G06F13/364 ,  G06F13/385 ,  G06F15/7807 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: A microcontroller device has a housing with a plurality of external pins having a plurality of input/output pins, a first microcontroller with a first central processing unit (CPU), a first system bus coupled with the first CPU, first memory coupled with the first system bus, and a first plurality of peripheral devices coupled with the first system bus, a second microcontroller with a second central processing unit (CPU), a second system bus coupled with the second CPU, second memory coupled with the second system bus, and a second plurality of peripheral devices coupled with the second system bus, and a pad ownership multiplexer unit being controllable to assign control of the input/output pins to either the first microcontroller or the second microcontroller, wherein the number of external pins is less than the sum of a data bus width of the first and second microcontroller.

Abstract translation: 微控制器装置具有壳体，多个外部引脚具有多个输入/输出引脚，具有第一中央处理单元（CPU）的第一微控制器，与第一CPU耦合的第一系统总线，与第一中央处理单元 系统总线和与第一系统总线耦合的第一多个外围设备，具有第二中央处理单元（CPU）的第二微控制器，与第二CPU耦合的第二系统总线，与第二系统总线耦合的第二存储器，以及 与第二系统总线耦合的第二多个外围设备，以及焊盘所有权复用器单元，其可控制以将输入/输出引脚的控制分配给第一微控制器或第二微控制器，其中外部引脚的数量小于 第一和第二微控制器的数据总线宽度之和。

公开(公告)号：WO0039821A3

公开(公告)日：2000-10-26

申请号：PCT/US9930528

申请日：1999-12-20

Applicant: MICROCHIP TECH INC

Inventor： YACH RANDY L ,  WOJEWODA IGOR

IPC: H01G4/38 ,  H01L27/08 ,  H01L29/92

CPC classification number: H01L27/0805

Abstract: A matching capacitor array is implemented on a single, monolithic integrated circuit. The array fastures a matrix of bottom electrodes and a plurality of continuous top electrode strips, where each continuous top electrode strip spans numerous bottom electrodes. The conductive contacts for each continuous top electrode strip are removed from the capacitor interface to the terminal ends of each of the continuous top electrode strips. The invention seeks to match or control parasitic and fringe capacitance, rather than to eliminate or minimize such capacitances. By creating a matched array, the parasitic and fringe capacitances of each matching capacitor unit cell are incorporated into the total capacitance of the unit cell.

Abstract translation: 匹配的电容器阵列在单个单片集成电路上实现。 该阵列固定了底部电极和多个连续顶部电极条的矩阵，其中每个连续的顶部电极条跨越许多底部电极。 每个连续顶部电极条的导电触点从电容器接口移除到每个连续顶部电极条的末端。 本发明寻求匹配或控制寄生和边缘电容，而不是消除或最小化这种电容。 通过创建匹配的阵列，每个匹配电容器单元的寄生和边缘电容被并入到单元的总电容中。