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    Semiconductor device comprises strip fuse with extremity connected to integrated component and intermediate streamer thermal dissipation element
    21.
    发明专利
    Semiconductor device comprises strip fuse with extremity connected to integrated component and intermediate streamer thermal dissipation element 未知

    公开(公告)号：FR2826509A1

    公开(公告)日：2002-12-27

    申请号：FR0108427

    申请日：2001-06-26

    Applicant: ST MICROELECTRONICS SA

    Inventor： FOURNEL RICHARD ,  CANDELIER PHILIPPE ,  COLOMBET NORBERT

    IPC: H01L23/367 ,  H01L23/525 ,  H01L23/552

    Abstract: The multilayer semiconductor device (1) of integrated electronic components comprises at least one electrical connection strip constituting a strip-fuse (2) in at least one layer, laid out so that it can be severed and whose extremity is connected to at least one integrated electronic component (4), and intermediate elements (5) for electrical connection and thermal dissipation. The intermediate elements (5) comprise at least one electrical connection strip extending in the form of a streamer (11), which is connected to the strip-fuse (2), through the thermal dissipation elements (6). The device also comprises a thermal screen (13) which is electrically insulated and placed in the immediate neighborhood of the strip-fuse (2), between the strip-fuse and the integrated electronic component. The intermediate elements (5) comprise the thermal dissipation strips (7) extending in different layers and connected by feedthroughs (8), in particular in a direction parallel to the strip-fuse. The screen (13) extends between the strip-fuse (2) and the intermediate elements (5), and the intermediate elements extensions (9) cross the screen (13). The screen (13) comprises strips spaced one from another and extended in different layers, placed one above another and connected by feedthroughs (15); this strip-screen extends perpendicular to the strip-fuse (2). The device comprises at least one protection diode (16) connected to the intermediate elements for electrical connection. The strip-fuse (2) can be severed by a laser beam directed to the bottom of a cavity (18).

    22.
    发明专利
    未知

    公开(公告)号：FR2787922A1

    公开(公告)日：2000-06-30

    申请号：FR9816582

    申请日：1998-12-23

    Applicant: ST MICROELECTRONICS SA

    Inventor： CANDELIER PHILIPPE ,  SCHOELLKOPF JEAN PIERRE

    IPC: G11C11/404 ,  H01L21/8246 ,  H01L27/112 ,  H01L27/115

    Abstract: The proposed memory cell on the basis of complementary metal-oxide semiconductor (CMOS) technology comprises a capacitor (C) associated in series with an asymmetric programming transistor (T) having the drain region which is weakly doped and of greater thickness than that of the source (s). The series connection of the capacitor (C) and the transistor (T) is between terminals of a voltage supply, the positive voltage terminal (13) and the ground. The gate (g) of transistor (T) is connected for an input of the selection signal, and the capacitor (C) with terminals (1,2) is connected between the positive voltage terminal (13) and the drain of transistor. The first electrode (2) of the capacitor (C) is constituted by the drain region. The capacitor (C) is formed in an oxide layer constituting the gate of transistors. The second electrode (1) of the capacitor (C) is connected to the positive voltage terminal to receive in reading or decoding a relatively low potential (Vdd), and in programming a relatively high potential (Vprog). The transistor (T) and the capacitor (C) are dimensioned so that, in the course of a programming cycle and for a non-selected cell, the voltage of the capacitor remains below the breakdown voltage, when currents in the capacitor and the transistor are in balance. The transistor (T) is dimensioned to limit the current in the selected cell, which allows the breakdown in the oxide layer constituting the capacitor (C). The manufacturing process for the memory cell of anti fusible type employing the CmOS technology, consists in the formation of the regions of the drain of the asymmetric transistors with p-type conductivity channels, and simultaneously a well for receiving the MOS transistors with n-type conductivity channels. In an embodiment of the memory cell in an architecture with a stage for differential reading, the circuit comprises two proposed memory cells connected by two NMOS transistors to the same reading amplifier, which comprises two inverters in antiparallel connection and two output inverters.

    Mémoire de puce électronique
    24.
    发明专利
    Mémoire de puce électronique 未知

    公开(公告)号：FR3091018A1

    公开(公告)日：2020-06-26

    申请号：FR1873830

    申请日：2018-12-21

    Applicant: ST MICROELECTRONICS SA

    Inventor： DENORME STÉPHANE ,  CANDELIER PHILIPPE

    IPC: H01L27/115 ,  G06F7/58 ,  H04L9/10

    Abstract: Mémoire de puce électronique La présente description concerne un dispositif (300) comprenant : au moins trois cellules mémoire (110) ; pour chaque cellule, une première région semiconductrice dopée (234) et un interrupteur (120) reliant la cellule à la première région ; et des premières zones semiconductrices dopées (302) connectant ensemble les premières régions (234). Figure pour l'abrégé : Fig. 3

    PROCEDE DE REALISATION DE CELLULES MEMOIRES DU TYPE A PROGRAMMATION UNIQUE COMPORTANT DES CONDENSATEURS MOS ET CIRCUIT INTEGRE CORRESPONDANT
    25.
    发明专利
    PROCEDE DE REALISATION DE CELLULES MEMOIRES DU TYPE A PROGRAMMATION UNIQUE COMPORTANT DES CONDENSATEURS MOS ET CIRCUIT INTEGRE CORRESPONDANT 未知

    公开(公告)号：FR3036530A1

    公开(公告)日：2016-11-25

    申请号：FR1554457

    申请日：2015-05-19

    Applicant: ST MICROELECTRONICS SA

    Inventor： DENORME STEPHANE ,  CANDELIER PHILIPPE

    IPC: G11C17/16

    Abstract: Circuit intégré comprenant un substrat (10) du type silicium sur isolant possédant un film semiconducteur (20n,p) situé au-dessus d'une couche isolante enterrée (30), au moins une cellule mémoire du type à programmation unique comportant un condensateur MOS (C) possédant une première région d'électrode (E1) incluant une région de grille (G) au moins partiellement siliciurée (ZSE1) et flanquée d'une région latérale isolante (CI1, CI2, CI4 et CI5), une couche diélectrique (OX) située entre la région de grille (G) et le film semiconducteur (20n et 20p), et une deuxième région d'électrode (E2) incluant une zone siliciurée (ZSE2) du film semiconducteur située à côté de ladite région latérale isolante (CI1, CI2, CI4 et CI5), et s's'étendant au moins partiellement sous la couche diélectrique (OX).

    28.
    发明专利
    未知

    公开(公告)号：DE60330130D1

    公开(公告)日：2009-12-31

    申请号：DE60330130

    申请日：2003-01-31

    Applicant: ST MICROELECTRONICS SA

    Inventor： GENDRIER PHILIPPE ,  DRAY CYRILLE ,  FOURNEL RICHARD ,  POIRIER SEBASTIEN ,  CASPAR DANIEL ,  CANDELIER PHILIPPE

    IPC: H01L29/788 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/792

    Abstract: The semiconductor memory device comprises a transistor with floating gate (FG) and a control gate, where the regions of source (S), drain (D) and channel of the floating-gate transistor form the control gate, and the memory cell comprises a dielectric zone (ZTN) laid out between a part (P1) of the layer of gate material and an active semiconductor zone (RG1) electrically insulated from another active zone (RG2) incorporating the control gate. The dielectric zone forms a tunnel zone (ZTN) for transferring the charges stored in the floating gate at the time of erasing the memory cell. The capacitive value of tunnel zone (ZTN) is below or equal to 30% of the total capacitive value between the layer of gate material and the set of active zones of the memory cell. The transistor has a ring gate (FG), and the gate material comprises a linking part (PL) connecting the first part (P1) and the ring gate. The active zones (RG1,RG2) are electrically insulated by the p-n junctions polarized in reverse, and the two zones are electrically insulated on the surface by a region of shallow trench isolation (STI). A memory array comprises several memory cells, each memory cell is associated with an access transistor, and the access transistor partly surrounds the floating-gate transistor of the memory cell resulting in a memory array of reduced size and lower programming currents. The device comprises the polarization means possessing the states of programming, reading and erasing the memory cell, where the erasing is of type Fowler-Nordheim and applies a voltage on the first active zone which is much higher than that applied in the regions of source, drain and substrate of the transistor. The programming of type Fowler-Nordheim applies to the regions of source, drain and substrate of the transistor voltages which are much higher than those applied to the first active zone. In the reading state the difference between the drain/source voltages is limited to 1 V in absolute value. An integrated circuit comprises the device as claimed.

    29.
    发明专利
    未知

    公开(公告)号：AT449424T

    公开(公告)日：2009-12-15

    申请号：AT03709915

    申请日：2003-01-31

    Applicant: ST MICROELECTRONICS SA

    Inventor： GENDRIER PHILIPPE ,  DRAY CYRILLE ,  FOURNEL RICHARD ,  POIRIER SEBASTIEN ,  CASPAR DANIEL ,  CANDELIER PHILIPPE

    IPC: H01L29/788 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/792

    Abstract: The semiconductor memory device comprises a transistor with floating gate (FG) and a control gate, where the regions of source (S), drain (D) and channel of the floating-gate transistor form the control gate, and the memory cell comprises a dielectric zone (ZTN) laid out between a part (P1) of the layer of gate material and an active semiconductor zone (RG1) electrically insulated from another active zone (RG2) incorporating the control gate. The dielectric zone forms a tunnel zone (ZTN) for transferring the charges stored in the floating gate at the time of erasing the memory cell. The capacitive value of tunnel zone (ZTN) is below or equal to 30% of the total capacitive value between the layer of gate material and the set of active zones of the memory cell. The transistor has a ring gate (FG), and the gate material comprises a linking part (PL) connecting the first part (P1) and the ring gate. The active zones (RG1,RG2) are electrically insulated by the p-n junctions polarized in reverse, and the two zones are electrically insulated on the surface by a region of shallow trench isolation (STI). A memory array comprises several memory cells, each memory cell is associated with an access transistor, and the access transistor partly surrounds the floating-gate transistor of the memory cell resulting in a memory array of reduced size and lower programming currents. The device comprises the polarization means possessing the states of programming, reading and erasing the memory cell, where the erasing is of type Fowler-Nordheim and applies a voltage on the first active zone which is much higher than that applied in the regions of source, drain and substrate of the transistor. The programming of type Fowler-Nordheim applies to the regions of source, drain and substrate of the transistor voltages which are much higher than those applied to the first active zone. In the reading state the difference between the drain/source voltages is limited to 1 V in absolute value. An integrated circuit comprises the device as claimed.

    PROCEDE DE CONTROLE DU FONCTIONNEMENT D'UNE POMPE DE CHARGE ET CIRCUIT INTEGRE DE POMPE DE CHARGE CORRESPONDANT
    30.
    发明专利
    PROCEDE DE CONTROLE DU FONCTIONNEMENT D'UNE POMPE DE CHARGE ET CIRCUIT INTEGRE DE POMPE DE CHARGE CORRESPONDANT 未知

    公开(公告)号：FR2884072A1

    公开(公告)日：2006-10-06

    申请号：FR0503204

    申请日：2005-04-01

    Applicant: ST MICROELECTRONICS SA

    Inventor： CANDELIER PHILIPPE ,  PILLONNET GAEL

    IPC: H02M3/07 ,  H03K17/16

    Abstract: Procédé de contrôle du fonctionnement d'une pompe de charge comprenant au moins un étage (Et) de pompe de charge comportant un réseau de transistors principaux NMOS (Res1) et PMOS (Res2) et deux condensateurs de transfert (capaH, capaL) possédant chacun une première borne pour recevoir un signal de commande (clk, clkb) et une deuxième borne connectée au réseau de transistors principaux (Res1, Res2). On polarise le substrat de chaque transistor principal NMOS (NMOSP1, NMOSP2) avec une tension de polarisation égale au minimum des tensions présentes aux deuxièmes bornes des condensateurs (capaH, capaL), et on polarise le substrat de chaque transistor principal PMOS avec une tension de polarisation égale au maximum des tensions présentes aux deuxièmes bornes des condensateurs (capaH, capaL).

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