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公开(公告)号：DE69825558D1
公开(公告)日：2004-09-16
申请号：DE69825558
申请日：1998-03-31
Applicant: ST MICROELECTRONICS SRL
Inventor： PORTALURI SALVATORE , PISATI VALERIO , ZANGRANDI LUIGI
IPC: H03K7/08
Abstract: A device for generating pulses of high-precision programmable duration, whose particularity is the fact that it comprises: -- first pulse generator means (1) which are suitable to receive in input a pulse generation command signal (IN) and to emit in output a first pulse for loading the contents of a register in counter means (2); -- second pulse generator means (4), triggered by the first pulse in output from the first pulse generator means (1); -- third pulse generator means (6), triggered by a second pulse emitted by the second pulse generator means and suitable to generate a third pulse to restart the second pulse generator means; the second pulse emitted by the second pulse generator means (4) constituting a clock signal for the counter means (2) in order to produce a decrement in the counter means; the signal in output from the counter means (2) being the pulsed signal to be generated (OUT); the duration of the pulsed signal being determined by the content of the counter means (2).
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公开(公告)号：DE69824143D1
公开(公告)日：2004-07-01
申请号：DE69824143
申请日：1998-03-31
Applicant: ST MICROELECTRONICS SRL
Inventor： MARCHESE STEFANO , PISATI VALERIO , PORTALURI SALVATORE , SAVO ALESSANDRO
Abstract: An amplifier with programmable gain and input linearity, comprising an input stage (10), which is suitable to receive a voltage signal (V , V ) and perform current conversion thereof with compression, and an output stage (30), which is connected to the input stage (10) and is suitable to decompress the signal in output from the input stage, producing gain amplification thereof; the particularity of the amplifier is the fact that it further comprises at least one current amplifier stage (20) which is interposed between the input stage (10) and the output stage (30) and comprises at least one bipolar transistor (21, 22) which is series-connected to a load diode (23, 24) and to a current source (2I2); programmable means (I2, I2*) for reducing the transconductance of the load diode (23, 24) being provided in the at least one amplifier stage (20) to determine a programmable amplification factor for the gain of the amplifier.
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公开(公告)号：DE69529397D1
公开(公告)日：2003-02-20
申请号：DE69529397
申请日：1995-02-22
Applicant: ST MICROELECTRONICS SRL
Inventor： ALINI ROBERTO , BRIANTI FRANCESCO , PISATI VALERIO , DEMICHELI MARCO
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公开(公告)号：DE69624460D1
公开(公告)日：2002-11-28
申请号：DE69624460
申请日：1996-01-26
Applicant: ST MICROELECTRONICS SRL , CONS RIC MICROELETTRONICA
Inventor： ALINI ROBERTO , BRUCCOLERI MELCHIORRE , COSENTINO GAETANO , PISATI VALERIO
Abstract: The amplifier described has an output stage constituted by an npn transistor (Q1) and a pnp transistor (Q2) in a push-pull arrangement, and a driver stage. The latter comprises a current-mirror circuit having, in its input branch, a pnp transistor (Q3) in series with a first constant-current generator (G1) and, in its output branch, an npn transistor (Q4), and two complementary transistors (Q5 and Q6) of which the collectors are connected together to the output terminal (OUT) and the bases are connected together to the input terminal (IN) of the amplifier. The emitter of the pnp transistor (Q5) of the driver stage is connected to the positive terminal (vdd) of the supply by means of a second constant-current generator (G2) and to the base of the npn transistor (Q1) of the output stage, and the emitter of the npn transistor (Q6) of the driver stage is connected to the negative terminal (gnd) of the supply by means of the npn transistor (Q4) of the output branch of the current-mirror circuit and to the base of the pnp transistor (Q2) of the output stage. The amplifier has a very low or zero offset (Vos = Vout-Vin).
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公开(公告)号：DE69520562D1
公开(公告)日：2001-05-10
申请号：DE69520562
申请日：1995-05-15
Applicant: ST MICROELECTRONICS SRL
Inventor： BRUCCOLERI MELCHIORRE , DEMICHELI MARCO , PATTI GIUSEPPE , PISATI VALERIO
Abstract: A digital/analog quadratic converter (DACQ) composed by a pair of linear converters connected in cascade has a direct coupling of the output node of the first converter (DAC1) with a node of a R-2R type resistive network of the second converter (DAC2) corresponding to the LSB stage of the R-2R type resistive network. High impedance nodes, notably the input node of the second linear converter, are advantageously eliminated from the "current path" thus markedly reducing the problems of relatively long settling times of high impedance nodes (having intrinsically large parasitic capacitances associated therewith). The peculiar architecture of the quadratic converter provides also for a remarkable simplification of the circuit.
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Patent Agency Ranking
公开(公告)号：ITMI990350A1
公开(公告)日：2000-08-21
申请号：ITMI990350
申请日：1999-02-19
Applicant: ST MICROELECTRONICS SRL
Inventor： PISATI VALERIO , PORTALURI SALVATORE , MARCHESE STEFANO , SAVO ALESSANDRO
IPC: H03G1/00
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公开(公告)号：DE69421072T2
公开(公告)日：2000-04-20
申请号：DE69421072
申请日：1994-05-23
Applicant: ST MICROELECTRONICS SRL
Inventor： ZUFFADA MAURIZIO , GADDUCCI PAOLO , MOLONEY DAVID , PISATI VALERIO
Abstract: The device is to be used with a parallel architecture PRML reading apparatus comprising a variable-gain input amplifier (21), a low-pass analog filter (22), a transversal analog filter (23) and two distinct and parallel processing channels (24, 34) interposed between the transversal analog filter (23) and an RLL-NRZ decoder (25). The two processing channels (24, 34) comprise respective analog-digital converters (26, 36) and respective Viterbi detectors (27, 37) and operate according to sampling sequences that alternate with one another. The device (30) for processing the servo signals comprises a rectifier (31) connected to the outputs of said analog-digital converters (26, 36) and an integrator (32).
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公开(公告)号：DE69421072D1
公开(公告)日：1999-11-11
申请号：DE69421072
申请日：1994-05-23
Applicant: ST MICROELECTRONICS SRL
Inventor： ZUFFADA MAURIZIO , GADDUCCI PAOLO , MOLONEY DAVID , PISATI VALERIO
Abstract: The device is to be used with a parallel architecture PRML reading apparatus comprising a variable-gain input amplifier (21), a low-pass analog filter (22), a transversal analog filter (23) and two distinct and parallel processing channels (24, 34) interposed between the transversal analog filter (23) and an RLL-NRZ decoder (25). The two processing channels (24, 34) comprise respective analog-digital converters (26, 36) and respective Viterbi detectors (27, 37) and operate according to sampling sequences that alternate with one another. The device (30) for processing the servo signals comprises a rectifier (31) connected to the outputs of said analog-digital converters (26, 36) and an integrator (32).
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公开(公告)号：IT1316796B1
公开(公告)日：2003-05-12
申请号：ITMI20000469
申请日：2000-03-09
Applicant: ST MICROELECTRONICS SRL
Inventor： PISATI VALERIO , DEMICHELI MARCO , BRUCCOLERI MELCHIORRE
Abstract: A circuit device for restoring the symmetry of an analog signal originated by the reading of data from magnetic supports, including at least one differential cell multiplier whose cell includes a pair of input MOS transistors having respective conduction terminals linked together at a circuit node. Advantageously, provided in parallel with each of the cell input transistors, are a plurality of transistors individually connectable to and disconnectable from each of the input transistors by corresponding switches.
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公开(公告)号：IT1316690B1
公开(公告)日：2003-04-24
申请号：ITMI20000393
申请日：2000-02-29
Applicant: ST MICROELECTRONICS SRL
Inventor： PISATI VALERIO , PORTALURI SALVATORE , CAZZANIGA MARCO , CASTELLO RINALDO
Abstract: This invention relates to a circuit structure of the feedforward type with programmable zeroes, particularly for synthesizing time-continual filters. This structure comprises a pair of amplification cells (14,15) interconnected at at least one interconnection node (A) and connected between a first signal (Vin) input (IN) of a first cell (14) and an output terminal (U) of the second cell (15, each cell (14,15) comprising a pair of transistors (10,2;6,7) which have a conduction terminal in common and have the other conduction terminals coupled respectively to a first voltage reference (Vcc) through respective bias members (3,4;9,11). The structure further comprises a circuit leg (13) connecting a node (X) of the first cell (14) to the output terminal (U) and comprising a transistor (8) which has a control terminal connected to the node (X) of the first cell (14), a first conduction terminal connected to the output terminal (U), and a second conduction terminal coupled to a second voltage reference (GND) through a capacitor (Cc). Thus, a released "zero" can be introduced in the right semiplane of the pole-zero complex plane to improve the flattening of group gain.
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