Abstract:
PURPOSE: A thin film transistor, an organic electroluminescent display device including the same and manufacturing methods thereof are provided to improve the property of a semiconductor layer by controlling metal silicide due to metal catalyst. CONSTITUTION: A semiconductor layer includes one or more channel regions and a source/drain region on a buffer layer. A gate insulation layer is located on the substrate. A gate electrode(150) is located on the gate insulation layer. An interlayer insulation layer(160) is located on the substrate. Source and drain electrodes(170a,170b) are located on the interlayer insulation layer and are electrically connected to the semiconductor layer. A polycrystalline silicon layer of the channel region of the semiconductor layer includes only the low angle grain boundary. A high angle grain boundary is located on the region except the channel region of the semiconductor layer.
Abstract:
PURPOSE: A sputtering apparatus is provided to uniformly deposit metallic catalyst of very low density on a substrate by reducing the unevenness of a metallic catalyst which is deposited at the edge of the substrate. CONSTITUTION: In a sputtering apparatus, a metal target(120) is arranged in a reaction chamber. The area of the metal target is at least 1.3 times larger than that of the substrate mounted in a substrate holder. A substrate holder(130) is arranged to be faced with the metal target. A vacuum pump(140) is connected to the exhaust pipe of the reaction chamber. A first shield(160) controls the progressive direction of the metallic catalyst discharged from the metal target.
Abstract:
PURPOSE: A source gas supplying unit, a deposition device having the same and a method thereof are provided to deposit a uniform thin by supplying a source gas to deposition chamber. CONSTITUTION: In a source gas supplying unit, a deposition device having the same and a method thereof, a source is stored in a canister(112). A heating portion heats the canister. A source gas supply tube(114) is formed in one side of the canister. A measuring unit is installed in the source gas supply tube and measures the amount of the source gas through a source gas supply tube. A temperature controller(116) is connected to a heating unit and the measuring unit. The temperature controller controls the heating unit according the amount of the source gas.
Abstract:
PURPOSE: Inline thermal process equipment and a wafer thermal processing method using the same are provided to increase the crystallinity of polysilicon by rapidly heat-treating a substrate at a high temperature more than a strain point of substrate. CONSTITUTION: A rapid thermal anneal part comprises a rapid high temperature annealing unit(600), a heating source(610) and a second controller. The heating source is installed inside the rapid high temperature annealing unit. The second controller controls the temperature value of the heating source. The second controller controls the operation of the heating source in order to heat the substrate(10) with rapid annealing temperature value.
Abstract:
PURPOSE: A substrate heat treatment system is provided to reduce a space and equipment by forming a chamber of a thermal treatment apparatus as a multi-layer structure without an additional transfer unit. CONSTITUTION: A heat treatment of substrate system comprises a thermal treatment unit(10) and a transfer unit(20). A thermal treatment unit includes at least one chamber(10a,10b,10c) with a heating unit(11a,11b,11c) for processing a substrate through thermal treatment. The transport unit is installed at the one side of the thermal treatment unit and supports the substrate before and after thermal treatment and transfers it. The chambers are deposited in a vertical direction, and the same process is performed in the chamber.
Abstract:
A method of crystallizing a silicon layer and a method of manufacturing a TFT, the method of crystallizing a silicon layer including forming a catalyst metal layer on a substrate; forming a catalyst metal capping pattern on the catalyst metal layer; forming a second amorphous silicon layer on the catalyst metal capping pattern; and heat-treating the second amorphous silicon layer to form a polycrystalline silicon layer.
Abstract:
온전류의 크기를 유지하면서 누설전류를 줄일 수 있는 박막 트랜지스터를 개시한다. 본 발명에 의한 박막 트랜지스터는 기판; 양끝단의 소스 영역 및 드레인 영역, 상기 소스 영역 또는 상기 드레인 영역에 인접한 저농도 도핑영역, 적어도 둘 이상의 채널영역, 상기 채널영역 사이의 고농도 도핑영역을 포함하는 상기 기판 위의 활성층; 상기 활성층 위의 게이트 절연막; 적어도 둘 이상의 개별 게이트 전극을 포함하고, 상기 개별 게이트 전극 아래에 채널영역이 위치하고, 최외각의 상기 개별 게이트 전극의 바깥쪽으로 상기 소스 영역 및 상기 드레인 영역이 위치한 상기 게이트 절연막 위의 다중 게이트 전극; 상기 다중 게이트 전극 위의 제1 층간 절연막; 및 상기 제1 층간 절연막을 관통하여 상기 소스 영역과 상기 드레인 영역에 각각 접촉하는 소스 전극 및 드레인 전극; 을 포함한다.
Abstract:
PURPOSE: A method for forming a polycrystalline silicon layer and a method for forming a thin film transistor using the same are provided to control a leakage current and leakage current dissemination of the thin film transistor by controlling the location and number of a grain boundary within the polycrystalline silicon. CONSTITUTION: A buffer layer is formed on a substrate(S110). A catalyst metal layer is formed on the buffer layer(S120). A first amorphous silicon layer is formed on the catalyst metal layer(S130). A catalyst metal capping pattern is formed by patterning the first amorphous silicon layer(S140). The thermal process is executed in 300-500°C range. The catalyst metal layer which is formed on a domain except for the catalyst metal capping pattern is eliminated when patterning the first amorphous silicon layer. A second amorphous silicon layer is formed on the catalyst metal capping pattern and the buffer layer(S150). The second amorphous silicon layer is crystallized by a thermal process(S160).