公开(公告)号：KR1020130094107A

公开(公告)日：2013-08-23

申请号：KR1020120015514

申请日：2012-02-15

Applicant: 삼성전자주식회사

Inventor： 김재춘 ,  권흥규 ,  김영득 ,  김지철 ,  변재범 ,  송호건 ,  조은석

IPC: H01L23/34

CPC classification number: H01L23/36 ,  H01L23/3128 ,  H01L23/42 ,  H01L23/49816 ,  H01L25/0657 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/15311 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/00

Abstract: PURPOSE: A semiconductor package including a heat spreader and a forming method thereof are provided to improve heat discharge efficiency by forming a second heat spread pattern with a thermal interface material between a semiconductor chip and a first heat spread pattern. CONSTITUTION: A semiconductor chip (41) is mounted on a substrate (21). A first heat spread pattern (29) is mounted on the substrate. The first heat spread pattern includes an opening part to expose the semiconductor chip. A second heat spread pattern (32) is formed between the side of the semiconductor chip and the first heat spread pattern. The second heat spread pattern includes a thermal interface material.

Abstract translation: 目的：提供一种包括散热器及其形成方法的半导体封装，通过在半导体芯片和第一扩散图案之间形成具有热界面材料的第二热扩散图案来提高散热效率。 构成：将半导体芯片（41）安装在基板（21）上。 第一散热图案（29）安装在基板上。 第一扩散图案包括露出半导体芯片的开口部分。 在半导体芯片的一侧和第一扩散图案之间形成第二扩散图案（32）。 第二热扩散图案包括热界面材料。

公开(公告)号：KR1020120104666A

公开(公告)日：2012-09-24

申请号：KR1020110022201

申请日：2011-03-14

Applicant: 삼성전자주식회사

Inventor： 한일영 ,  송호건 ,  박상욱 ,  홍지석

IPC: H01L23/48 ,  H01L21/60

CPC classification number: H01L21/67092 ,  H01L21/6835 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/799 ,  H01L24/94 ,  H01L24/96 ,  H01L24/98 ,  H01L25/0652 ,  H01L2221/6834 ,  H01L2221/68372 ,  H01L2221/68381 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2224/7999 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/12042 ,  H01L2924/14 ,  Y10T156/11 ,  Y10T156/19 ,  H01L2224/81 ,  H01L2924/00

Abstract: PURPOSE: A debonding device for semiconductor manufacture is provided to remarkably reduce shear force required for a debonding process, thereby minimizing bump damage of a chip. CONSTITUTION: A chuck(120) which is possible to access or separate for a stage is arranged in an upper area of the stage. Chip stack assembly is chucked by the chuck. An up/down driving unit(130) is connected to the chuck and drives the chuck in up and down. A sliding driving unit(140) slides the chuck along to a side direction of a carrier wafer. A controller controls an operation of the up/down driving unit and the sliding driving unit for sliding the chip stack assembly after the controller moves the chip stack assembly to an upper direction for the carrier wafer.

Abstract translation: 目的：提供用于半导体制造的剥离装置，以显着降低剥离过程所需的剪切力，从而最小化芯片的凸起损坏。 构成：可以在舞台上进入或分离的卡盘（120）布置在舞台的上部区域中。 芯片堆叠组件被卡盘卡住。 上下驱动单元（130）连接到卡盘并且上下驱动卡盘。 滑动驱动单元（140）沿着载体晶片的侧面方向滑动卡盘。 控制器控制上/下驱动单元和滑动驱动单元的操作，以便在控制器将芯片堆叠组件移动到载体晶片的上方向之后滑动芯片堆叠组件。

公开(公告)号：KR1020120095692A

公开(公告)日：2012-08-29

申请号：KR1020110015162

申请日：2011-02-21

Applicant: 삼성전자주식회사

Inventor： 정세영 ,  조태제 ,  송호건 ,  이규하

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/768 ,  H01L23/14 ,  H01L23/31 ,  H01L21/48 ,  H01L21/683 ,  H01L25/065 ,  H01L25/10

CPC classification number: H01L21/76898 ,  H01L21/486 ,  H01L21/6835 ,  H01L23/147 ,  H01L23/3128 ,  H01L23/3171 ,  H01L23/3192 ,  H01L23/49827 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/105 ,  H01L2221/68327 ,  H01L2221/68331 ,  H01L2221/6834 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05109 ,  H01L2224/05139 ,  H01L2224/05144 ,  H01L2224/05147 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/05569 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05572 ,  H01L2224/06181 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/16146 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16237 ,  H01L2224/17181 ,  H01L2224/48157 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/81815 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L21/64 ,  H01L23/045 ,  H01L23/48 ,  H01L2924/014 ,  H01L2224/05552 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to obtain improved electrical property and reliability by selectively forming an insulation layer on one surface of a semiconductor substrate at low costs with a simple process. CONSTITUTION: A substrate(10) having a first surface(11) and a second surface is prepared. A passivation layer(15) for exposing a part of a pad(14) is formed on the first surface of the substrate. A via hole(16) is formed to expose at least a part of the substrate from the first surface. A via hole insulation layer(22) is formed on a side wall of the via hole. A through-electrode(20) is formed in the via hole. The through-electrode comprises a barrier layer(24) and a conductive connection part(26).

Abstract translation: 目的：提供一种半导体器件及其制造方法，通过简单的工艺以低成本选择性地在半导体衬底的一个表面上形成绝缘层，以获得改进的电性能和可靠性。 构成：制备具有第一表面（11）和第二表面的基底（10）。 在衬底的第一表面上形成用于暴露焊盘（14）的一部分的钝化层（15）。 形成通孔（16）以使基板的至少一部分从第一表面露出。 通孔绝缘层（22）形成在通孔的侧壁上。 在通孔中形成贯通电极（20）。 通孔包括阻挡层（24）和导电连接部分（26）。

公开(公告)号：KR1020120038811A

公开(公告)日：2012-04-24

申请号：KR1020100100467

申请日：2010-10-14

Applicant: 삼성전자주식회사

Inventor： 정세영 ,  송호건 ,  이충선 ,  이호진

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/481 ,  H01L21/563 ,  H01L21/76898 ,  H01L23/3128 ,  H01L24/04 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/17 ,  H01L24/32 ,  H01L24/48 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2221/68372 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/13009 ,  H01L2224/13025 ,  H01L2224/1403 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73257 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/1304 ,  H01L2924/14 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19104 ,  H01L2924/00 ,  H01L2224/05552 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: PURPOSE: A semiconductor device and a manufacturing method thereof are provided to laminate a plurality of the semiconductor devices with different sizes by including penetration electrodes which have different protrusion heights from each other. CONSTITUTION: A semiconductor device comprises a first semiconductor chip(110a), a second semiconductor chip(120), and a third semiconductor chip(130). The first semiconductor chip comprises a first penetration electrode which has a first protrusion height and a second penetration electrode which has a second protrusion height. The second semiconductor chip is electrically connected to the first penetration electrode. The third semiconductor chip is electrically connected to the second penetration electrode.

Abstract translation: 目的：提供半导体器件及其制造方法，通过包括彼此不同的突起高度的穿透电极来层叠多个具有不同尺寸的半导体器件。 构成：半导体器件包括第一半导体芯片（110a），第二半导体芯片（120）和第三半导体芯片（130）。 第一半导体芯片包括具有第一突出高度的第一穿透电极和具有第二突出高度的第二穿透电极。 第二半导体芯片电连接到第一穿透电极。 第三半导体芯片电连接到第二穿透电极。

公开(公告)号：KR1020120000805A

公开(公告)日：2012-01-04

申请号：KR1020100061268

申请日：2010-06-28

Applicant: 삼성전자주식회사

Inventor： 고준영 ,  박재용 ,  김희석 ,  송호건

IPC: H01L21/56

CPC classification number: H01L21/52 ,  H01L21/56 ,  H01L21/565 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2225/06562 ,  H01L21/568

Abstract: PURPOSE: A method for molding a semiconductor package is provided to prevent fault of the semiconductor package due to the imperfect filling of molding resin by spreading liquid molding resin or molding resin powder on the upper side of a semiconductor chip in advance or arranging the molding resin of a sheet form. CONSTITUTION: A substrate(10) in which a semiconductor chip(20) is installed is prepared. The semiconductor chip comprises a plurality of semiconductor chips which are laminated as a step form. Liquid molding resin(31) is spread on the upper side of the semiconductor chip. The substrate is installed on a bottom mold(51). A top mold(52) is installed on the bottom mold. Fused molding resin(32) is inserted in a space between the bottom mold and the top mold. The thickness of a gap between the upper side of the semiconductor chip and the top mold is less than 150micrometer.

Abstract translation: 目的：提供一种用于模制半导体封装的方法，以通过预先将半导体芯片的上侧侧的液体模制树脂或模制树脂粉末铺展在模制树脂的不完全填充来防止半导体封装的故障，或者将成型树脂 的表格。 构成：准备安装有半导体芯片（20）的基板（10）。 半导体芯片包括作为台阶形式层压的多个半导体芯片。 液体模塑树脂（31）扩散在半导体芯片的上侧。 基板安装在底模51上。 顶模（52）安装在底模上。 熔融成型树脂（32）插入在底模和顶模之间的空间中。 半导体芯片的上侧和上模之间的间隙的厚度小于150微米。

公开(公告)号：KR1020090014038A

公开(公告)日：2009-02-06

申请号：KR1020070078264

申请日：2007-08-03

Applicant: 삼성전자주식회사

Inventor： 정석원 ,  김학성 ,  송호건

IPC: H01L21/60 ,  H01L23/488

CPC classification number: H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/00014

Abstract: A method of fabricating semiconductor device package is provided to improve the reliability of solder interconnection by reducing the amount of strain change in the solder interconnection unit due to the thermal expansion coefficient mismatch between a semiconductor package and a wiring board. In a method of fabricating semiconductor device package, a semiconductor package having outer lead is prepared. A wiring board(160) includes a bonding electrode(166) and protrusion(180), and the solder interconnection(170) is formed in the bonding electrode site. The semiconductor package is mounted on the wiring board by welding the solder interconnection with the outer lead. At this time, the protrusion is interposed between the semiconductor package and a wiring board , and the thickness of the solder interconnection is enlarged.

Abstract translation: 提供一种制造半导体器件封装的方法，通过减少由于半导体封装和布线板之间的热膨胀系数不匹配导致的焊料互连单元中的应变变化量，从而提高焊料互连的可靠性。 在制造半导体器件封装的方法中，制备具有外引线的半导体封装。 布线板（160）包括接合电极（166）和突起（180），并且在接合电极部位形成焊料互连（170）。 通过焊接与外引线的焊接互连，将半导体封装安装在布线板上。 此时，突起被插入在半导体封装和布线板之间，并且焊料互连的厚度增大。

公开(公告)号：KR100744147B1

公开(公告)日：2007-08-01

申请号：KR1020060079528

申请日：2006-08-22

Applicant: 삼성전자주식회사

Inventor： 한만희 ,  김근우 ,  김희석 ,  송호건

IPC: H01L21/58 ,  H05K13/02 ,  H05K13/04

Abstract: A semiconductor chip pickup assembly and a method for attaching a semiconductor chip are provided to improve bad attaching of the chip by independently applying a load to a center region and an edge region of the chip. A center head part(100) has a first contact surface(100S) contacting a center region(A) of a semiconductor chip(70) to apply a load to the center region, and is vertically moved. A periphery head part(200) has a second contact surface(200S) contacting an edge region of the semiconductor chip to apply a load to the edge, and is vertically moved independent of the center head part. The first contact surface is formed with at least one vacuum inlet, and the first and/or second contact surface is made of elastic material.

Abstract translation: 提供半导体芯片拾取组件和用于附接半导体芯片的方法，以通过独立地将负载施加到芯片的中心区域和边缘区域来改善芯片的不良附接。 中心头部（100）具有与半导体芯片（70）的中心区域（A）接触以向中心区域施加载荷并且垂直移动的第一接触表面（100S）。 外围头部（200）具有与半导体芯片的边缘区域接触以向边缘施加载荷的第二接触表面（200S），并且独立于中心头部分垂直移动。 第一接触表面形成有至少一个真空入口，并且第一和/或第二接触表面由弹性材料制成。

公开(公告)号：KR100734269B1

公开(公告)日：2007-07-02

申请号：KR1020050069662

申请日：2005-07-29

Applicant: 삼성전자주식회사

Inventor： 고준영 ,  송호건 ,  임재윤 ,  천대상

IPC: H01L23/48

CPC classification number: B23K20/007 ,  H01L24/45 ,  H01L24/48 ,  H01L24/78 ,  H01L24/85 ,  H01L2224/05554 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/78268 ,  H01L2224/78301 ,  H01L2224/786 ,  H01L2224/85045 ,  H01L2224/851 ,  H01L2224/85181 ,  H01L2224/85203 ,  H01L2224/85205 ,  H01L2224/85947 ,  H01L2924/01006 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/20104 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/20107 ,  H01L2924/20303 ,  H01L2924/20304 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00015

Abstract: 와이어 본딩시 가해지는 힘을 감소시켜, 본딩 패드의 손상 및 층간 절연막의 붕괴를 방지할 수 있는 와이어 본딩 장치를 개시한다. 개시된 본 발명의 와이어 본딩 장치를 이용하는 와이어 본딩 방법은, 캐필러리로부터 돌출된 와이어 선단에 접착 볼을 형성한다. 다음, 상기 접착 볼의 접착면을 디스크 형태로 변형시킨 다음, 상기 디스크 형태의 접착면을 갖는 접착 볼을 상기 본딩 패드에 본딩시킨다.
와이어 본딩, 접착 볼, 디스크, 저유전, 본딩 패드, 플레이트

公开(公告)号：KR1020070019809A

公开(公告)日：2007-02-15

申请号：KR1020050073732

申请日：2005-08-11

Applicant: 삼성전자주식회사

Inventor： 정기현 ,  김희석 ,  김상준 ,  신화수 ,  송호건 ,  고준영

IPC: H01L21/60 ,  H01L23/48

CPC classification number: H05K3/282 ,  H01L21/4853 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05548 ,  H01L2224/05567 ,  H01L2224/16503 ,  H01L2224/32057 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83102 ,  H01L2224/83385 ,  H01L2224/92125 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01077 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/181 ,  H05K3/243 ,  H05K3/3457 ,  H05K2201/0391 ,  H05K2201/0989 ,  H01L2924/00014 ,  H01L2924/00012

Abstract: 내열성이 우수하면서도 충격에 대한 특성이 우수한 솔더볼 랜드에 두 종류 이상의 표면처리부를 갖는 인쇄회로기판 및 이를 포함하는 반도체 패키지에 관해 개시한다. 이를 위해 본 발명은 솔더볼 랜드 표면에 두 종류 이상의 표면처리부를 갖는 인쇄회로기판과, 이를 이용한 솔더볼 랜드에 두 종류 이상의 금속접합층을 갖는 반도체 패키지를 제공한다. 2 종류 이상의 표면처리부는 인쇄회로기판 가장자리에는 OSP로 표면처리되고, 중앙에는 니켈과 골드층이 표면처리된 것을 사용할 수 있다. 또한 각각의 솔더볼 랜드에 대하여 가장자리에는 OSP 표면처리하고, 중앙에는 니켈과 골드층이 표면처리된 혼합 솔더볼 랜드를 사용할 수 있다.
OSP, 솔더볼 랜드, SJR, 금속접합층(IMC).

公开(公告)号：KR101831938B1

公开(公告)日：2018-02-23

申请号：KR1020110131696

申请日：2011-12-09

Applicant: 삼성전자주식회사

Inventor： 박진우 ,  송호건 ,  이석현

IPC: H01L23/12 ,  H01L23/48

CPC classification number: H01L21/568 ,  H01L21/561 ,  H01L23/02 ,  H01L23/04 ,  H01L23/053 ,  H01L23/055 ,  H01L23/057 ,  H01L23/08 ,  H01L23/12 ,  H01L23/13 ,  H01L23/24 ,  H01L23/3128 ,  H01L23/34 ,  H01L23/4926 ,  H01L23/49575 ,  H01L23/5389 ,  H01L24/13 ,  H01L24/24 ,  H01L24/73 ,  H01L24/82 ,  H01L24/96 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/24011 ,  H01L2224/24146 ,  H01L2224/32145 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73267 ,  H01L2224/82031 ,  H01L2224/82101 ,  H01L2224/96 ,  H01L2225/06524 ,  H01L2225/06548 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2225/06586 ,  H01L2924/12042 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/82 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: 본발명은팬 아웃웨이퍼레벨패키지의제조방법및 이에의해제조된팬 아웃웨이퍼레벨패키지를제공한다. 이방법에서는캐버티가형성된수용부를이용하여반도체칩들을적층할수 있어반도체칩들의쓰러짐을방지하여안정적으로적층구조의팬 아웃레벨패키지를제조할수 있다.