公开(公告)号：KR101746709B1

公开(公告)日：2017-06-14

申请号：KR1020100117666

申请日：2010-11-24

Applicant: 삼성전자주식회사

Inventor： 최석헌 ,  윤보언 ,  백재직 ,  조병권

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/32139 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78

Abstract: 금속게이트전극들을갖는반도체소자의제조방법이제공된다. 상기방법은제1 영역및 제2 영역을갖는반도체기판을준비하는것과, 상기반도체기판상에절연막을형성하는것을구비한다. 상기절연막은상기제1 및제2 영역들내에각각배치된제1 그루브및 제2 그루브를갖는층간절연막과상기제1 및제2 그루브들의적어도바닥면들을덮는게이트절연막을구비하도록형성된다. 상기절연막을갖는기판의전면상에적층금속막(laminated metal layer)을형성하고, 상기적층금속막상에비감광성(non-photo sensitivity)을갖는평탄화막을형성한다. 상기평탄화막은상기제1 및제2 그루브들을채우도록형성된다. 상기제1 영역내의상기평탄화막을건식식각공정을사용하여선택적으로제거하여, 상기제1 영역내의상기적층금속막을노출시키고상기제2 영역내의상기적층금속막을덮는평탄화막패턴을형성한다. 상기평탄화막패턴을형성하는동안상기제1 그루브내에제1 평탄화잔여물이형성될수 있다.

Abstract translation: 提供了一种制造具有金属栅电极的半导体器件的方法。 该方法包括制备具有第一区域和第二区域的半导体衬底，以及在半导体衬底上形成绝缘膜。 绝缘膜被形成为包括层间绝缘膜，该层间绝缘膜具有分别设置在第一区域和第二区域中的第一沟槽和第二沟槽以及覆盖第一沟槽和第二沟槽的至少底表面的栅极绝缘膜。 在具有绝缘膜的基板的前表面上形成层压金属层，并且在该层压金属膜上形成具有非光敏性的平坦化膜。 平坦化膜形成为填充第一和第二凹槽。 使用干蚀刻工艺选择性地去除第一区域中的平坦化膜，以暴露第一区域中的层压金属膜，并形成覆盖第二区域中的层压金属膜的平坦化膜图案。 在形成平坦化膜图案期间，可以在第一沟槽中形成第一平坦化残余物。

公开(公告)号：KR101635141B1

公开(公告)日：2016-07-08

申请号：KR1020090086084

申请日：2009-09-11

Applicant: 삼성전자주식회사

Inventor： 오세충 ,  김우진 ,  정준호 ,  임우창 ,  최석헌

IPC: G11C11/15 ,  H01L27/115

CPC classification number: G11C11/161

Abstract: 자기메모리소자가제공된다. 이자기메모리소자는기판및 기판상에차례로적층된하부자성체, 터널베리어, 및상부자성체를포함할수 있다. 하부자성체는기판에인접하게배치되고조밀육방격자(Hexagonal Close-Packing, HCP)구조를갖는하부수직자성층을포함할수 있다.

Abstract translation: 提供了一种磁存储元件。 磁存储器件可以包括衬底和依次堆叠在衬底上的下磁体，隧道势垒和上磁体。 下磁性体可以包括与衬底相邻设置并具有六方密堆积（HCP）结构的下垂直磁层。

公开(公告)号：KR101443063B1

公开(公告)日：2014-09-24

申请号：KR1020080069681

申请日：2008-07-17

Applicant: 삼성전자주식회사

Inventor： 최석헌 ,  이종원 ,  홍창기 ,  윤보언

IPC: H01L21/31 ,  H01L27/105

CPC classification number: H01L27/11507 ,  H01L21/3105 ,  H01L21/31053 ,  H01L28/55

Abstract: 향상된 특성을 갖는 강유전체 박막의 제조 방법 및 이를 이용한 반도체 장치의 제조 방법이 개시된다. 기판 상에 유기 금속 화학 기상 증착 공정으로 PZT를 증착하여 예비 강유전체막을 형성한 후, 예비 강유전체막의 표면을 아크릴산계 고분자, 연마입자 및 물을 포함하는 슬러리 조성물을 사용하여 화학 기계적으로 연마하여 기판 상에 강유전체 박막을 형성한다. 예비 강유전체막의 연마 속도를 감소시켜 벌크 부분의 연마를 억제하고 표면 거칠기를 개선함으로써, 강유전체 박막을 포함하는 메모리 장치의 전기적 특성 및 내구성을 향상시킬 수 있다.

公开(公告)号：KR1020130136788A

公开(公告)日：2013-12-13

申请号：KR1020120060472

申请日：2012-06-05

Applicant: 삼성전자주식회사

Inventor： 최석헌 ,  김진범

IPC: H01L21/336 ,  H01L29/78

CPC classification number: H01L29/66545

Abstract: Provided is a method for manufacturing a semiconductor device, capable of easily forming a gate pattern by using a dummy silicon electrode to change the concentration of carbon in a dummy gate which is formed before the gate pattern is formed. The method for manufacturing the semiconductor device includes the steps of: successively forming a first dummy gate insulation layer and a first dummy silicon electrode which includes a silicon layer doped with carbon on a substrate; and forming a second dummy silicon electrode on a second dummy gate insulation layer by trimming the first dummy silicon electrode, wherein the lower side of the second dummy silicon electrode is narrower than the upper side of the second dummy silicon electrode.

Abstract translation: 提供一种半导体器件的制造方法，其能够通过使用虚拟硅电极容易地形成栅极图案，以改变形成在栅极图案之前形成的伪栅极中的碳浓度。 制造半导体器件的方法包括以下步骤：在衬底上依次形成第一虚拟栅极绝缘层和第一虚拟硅电极，该第一虚设硅电极包括掺杂有碳的硅层; 以及通过对所述第一虚设硅电极进行微调而在第二伪栅极绝缘层上形成第二虚设硅电极，其中所述第二虚设硅电极的下侧比所述第二虚设硅电极的上侧窄。

公开(公告)号：KR1020120068057A

公开(公告)日：2012-06-27

申请号：KR1020100080955

申请日：2010-08-20

Applicant: 삼성전자주식회사

Inventor： 최석헌 ,  윤보언 ,  여인준 ,  한정남

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L21/28008 ,  H01L21/823807 ,  H01L21/823814 ,  H01L27/0629 ,  H01L28/20 ,  H01L29/66545

Abstract: PURPOSE: A semiconductor device and a fabricating method thereof are provided to improve reliability by arranging a passive device pattern on a floor side of a recess region lower than an upper portion of an active part. CONSTITUTION: A substrate includes a first transistor region, a second transistor region, and a passive device region. A device isolation pattern(102) defines a first active part(105a) within the first transistor region and a second active part(105b) within the second transistor region. A passive device pattern(125r) is arranged on a floor side of a recess region formed within the device isolation pattern of the passive device region and includes a semiconductor material The floor side of the recess region is lower than an upper side of the active part.

Abstract translation: 目的：提供半导体器件及其制造方法，以通过将无源器件图案布置在低于有源部分的上部的凹陷区域的地板侧上来提高可靠性。 构成：衬底包括第一晶体管区域，第二晶体管区域和无源器件区域。 器件隔离图案（102）限定第一晶体管区域内的第一有源部分（105a）和第二晶体管区域内的第二有源部分（105b）。 无源器件图案（125r）布置在形成在无源器件区域的器件隔离图案内的凹陷区域的地板侧上，并且包括半导体材料。凹陷区域的地板侧低于有源部分的上侧 。

公开(公告)号：KR1020120056112A

公开(公告)日：2012-06-01

申请号：KR1020100117666

申请日：2010-11-24

Applicant: 삼성전자주식회사

Inventor： 최석헌 ,  윤보언 ,  백재직 ,  조병권

IPC: H01L21/8238 ,  H01L21/28 ,  H01L21/3213 ,  H01L29/49 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L21/32139 ,  H01L21/28088 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78

Abstract: PURPOSE: A manufacturing method of a semiconductor device which includes metal gate electrodes is provided to completely eliminate an uppermost metal film arranged within a first region using a patterned planarization film as an etching mask, thereby forming first and second metal gates which have different work functions without process failure. CONSTITUTION: A semiconductor substrate(1) which has a first region(A) and a second region(B) is prepared. Gate insulating films(7a,7b) and an inter-layer insulating film(15) are formed on the semiconductor substrate. A laminated metal film(22) is formed on the front surface of the substrate which has the insulating film. A planarization film(23p) without photosensitive properties is formed on the laminated metal film. A planarization film pattern is formed within the second region for covering the laminated metal film.

Abstract translation: 目的：提供一种包括金属栅电极的半导体器件的制造方法，使用图案化的平坦化膜作为蚀刻掩模，完全消除了布置在第一区域内的最上面的金属膜，从而形成具有不同功函数的第一和第二金属栅极 没有过程故障。 构成：制备具有第一区域（A）和第二区域（B）的半导体衬底（1）。 栅极绝缘膜（7a，7b）和层间绝缘膜（15）形成在半导体衬底上。 在具有绝缘膜的基板的前表面上形成层压金属膜（22）。 在层叠的金属膜上形成没有光敏性的平坦化膜（23p）。 在用于覆盖层叠金属膜的第二区域内形成平坦化膜图案。

公开(公告)号：KR1020110021444A

公开(公告)日：2011-03-04

申请号：KR1020090079243

申请日：2009-08-26

Applicant: 삼성전자주식회사

Inventor： 손병근 ,  김한수 ,  안영수 ,  김민구 ,  김진호 ,  최재형 ,  최석헌

IPC: H01L27/115

CPC classification number: H01L27/11575 ,  H01L27/1157 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L27/0688 ,  H01L21/76897 ,  H01L27/2463 ,  H01L2924/00

Abstract: PURPOSE: A 3d semiconductor memory apparatus and a manufacturing method thereof are provided to obtain the forming margin of a contact plugs or wirings directly connected to the contact extensions by arranging the contact extensions and the even conductive patterns on the different contact areas. CONSTITUTION: A substrate(10) comprises a cell array region(CAR) and contact areas(CR1, CR2). An extrusion oxide(11) is arranged on the contact area of the substrate. A plurality of conductive patterns(GL1~GL6) is deposited with an interval on the substrate. The conductive pattern comprises a wire portion(IC) which is parallel to the substrate and a contact extension part(CT) being tilted to the substrate.

Abstract translation: 目的：提供3d半导体存储装置及其制造方法，以通过将接触延伸部和偶数导电图案布置在不同的接触区域上来获得直接连接到接触延伸部的接触插塞或布线的成形边缘。 构成：衬底（10）包括电池阵列区（CAR）和接触区（CR1，CR2）。 挤出氧化物（11）设置在基板的接触区域上。 多个导电图案（GL1〜GL6）在衬底上以间隔沉积。 导电图案包括平行于基板的导线部分（IC）和向基板倾斜的接触延伸部分（CT）。

公开(公告)号：KR1020100093354A

公开(公告)日：2010-08-25

申请号：KR1020090012502

申请日：2009-02-16

Applicant: 삼성전자주식회사

Inventor： 심현준 ,  김완돈 ,  최석헌 ,  이한신 ,  백인규 ,  자오진시 ,  임은경

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: H01L45/04 ,  G11C13/0004 ,  H01L29/513 ,  H01L29/517 ,  H01L45/1233

Abstract: PURPOSE: A method for manufacturing a resistance memory device is provided to form a resistance oxide layer which is physically and chemically stabilized without an etching process by forming the resistance oxide layer through the diffusion of oxygen to the upper surface of the first electrode through a second electrode. CONSTITUTION: A first electrode(12) is formed inside a lower insulation layer(10). A second electrode(14) is formed on a first electrode. The second electrode is formed on the deposition process using an organic metal precursor. The upper surface of the first electrode connected to the second electrode is converted into a resistance oxidation layer(16) by diffusing the oxygen to the upper surface of the first electrode through the second electrode.

Abstract translation: 目的：提供一种用于制造电阻存​​储器件的方法，以形成物理和化学稳定的电阻氧化层，无需蚀刻工艺，通过通过第二电极通过氧气扩散到第一电极的上表面形成电阻氧化物层 电极。 构成：第一电极（12）形成在下绝缘层（10）的内部。 在第一电极上形成第二电极（14）。 使用有机金属前体在沉积工艺上形成第二电极。 通过第二电极将氧扩散到第一电极的上表面，将连接到第二电极的第一电极的上表面转换成电阻氧化层（16）。

公开(公告)号：KR1020100085742A

公开(公告)日：2010-07-29

申请号：KR1020090005190

申请日：2009-01-21

Applicant: 삼성전자주식회사

Inventor： 남경태 ,  최석헌 ,  이장은 ,  오세충 ,  정준호

IPC: G11C11/15

CPC classification number: H01L27/228 ,  B82Y25/00 ,  G11C11/161 ,  G11C11/1675 ,  H01F10/3254 ,  H01F10/3268 ,  H01L43/08 ,  G11C11/155

Abstract: PURPOSE: A magnetic memory device is provided to reduce the magnetic coercivity of a free layer by heating the free layer of a magnetic tunnel junction structure including an electrode formed with silicon-germanium. CONSTITUTION: A magnetic tunnel junction structure comprises a free layer(150) on a semiconductor substrate(100). An electrode(172) is formed on the semiconductor substrate with silicon - germanium. The electrode heats the free layer to reduce the magnetic coercivity of the free layer. The content of the silicon - germanium is 10-57%. The silicon - germanium has a polycrystalline structure. The electrode is arranged on the magnetic tunnel junction structure. A top electrode is directly touched with the free layer.

Abstract translation: 目的：提供一种磁存储器件，通过加热包括由硅 - 锗形成的电极的磁性隧道结结构的自由层来降低自由层的磁矫顽力。 构成：磁性隧道结结构包括在半导体衬底（100）上的自由层（150）。 在半导体衬底上用硅 - 锗形成电极（172）。 电极加热自由层以降低自由层的磁矫顽力。 硅 - 锗的含量为10-57％。 硅 - 锗具有多晶结构。 电极布置在磁隧道结结构上。 顶部电极与自由层直接接触。

公开(公告)号：KR1020100082610A

公开(公告)日：2010-07-19

申请号：KR1020090001981

申请日：2009-01-09

Applicant: 삼성전자주식회사

Inventor： 조우진 ,  황재성 ,  최석헌 ,  김대겸 ,  김중현

IPC: G11C11/15 ,  H01L27/105

CPC classification number: H01L43/12 ,  G11C11/161 ,  G11C11/15 ,  H01L27/222 ,  H01L43/08

Abstract: PURPOSE: A method of forming a magnetic memory device is provided to prevent shorting of a magnetic memory cell by allowing an etch-byproducts to be contacted with a second magnetic conductor. CONSTITUTION: A first magnetic conductor(130), a tunnel barrier film(141), a second magnetic conductor(150) are successively formed on a substrate(110). A mask pattern is formed on the second magnetic conductor. A second magnetic conductor is etched by using a mask pattern as an etching mask. A spacer is formed on the sidewall of the second magnetic conductor. The first magnetic conductor is etched by using the mask pattern and spacer as an etching mask. A spacer is formed on the sidewall and a tunnel barrier rip of the second magnetic conductor.

Abstract translation: 目的：提供一种形成磁存储器件的方法，以通过允许蚀刻副产物与第二磁性导体接触来防止磁存储单元的短路。 构成：在衬底（110）上依次形成第一磁性导体（130），隧道势垒膜（141），第二磁性体（150）。 在第二磁性导体上形成掩模图形。 通过使用掩模图案作为蚀刻掩模蚀刻第二磁性导体。 间隔件形成在第二磁性导体的侧壁上。 通过使用掩模图案和间隔物作为蚀刻掩模蚀刻第一磁性导体。 在侧壁上形成间隔物，并形成第二磁性导体的隧道阻挡层。