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公开(公告)号：KR101250256B1
公开(公告)日：2013-04-03
申请号：KR1020110018777
申请日：2011-03-03
Applicant: 성균관대학교산학협력단
Abstract: 본 발명은 수직자기 기록매체의 자기기록층으로 사용되는 CoP 합금 박막을 제조하는 방법에 관한 것으로, 사카린(saccharine, C
7 H
5 NO
3 S)을 첨가한 도금용액에 시드층이 형성된 기판을 침지하고 전해 도금하다 상기 CoP 합금 박막을 형성하는 것을 특징으로 한다.
본 발명은, 전해도금 과정에서 첨가제를 첨가함으로써, 수직 이방성과 각형비가 크게 향상되어 수직자기 기록매체에 적용할 수 있는 CoP 합금 박막을 제조할 수 있는 효과가 있다.
또한, 본 발명의 제조방법으로 제조된 CoP 합금 박막은 재료비가 저렴하며 제조공정이 간단하여 수직자기 기록매체의 제조공정과 비용을 크게 낮출 수 있는 효과가 있다.-
公开(公告)号：KR1020130016502A
公开(公告)日：2013-02-18
申请号：KR1020110078478
申请日：2011-08-08
Applicant: 성균관대학교산학협력단
IPC: H01L33/48
CPC classification number: H01L33/647 , H01L23/142 , H01L23/49562 , H01L33/64 , H01L33/641 , H01L33/642 , H01L2224/48 , H01L2224/48091 , H01L2224/4918 , H01L2933/0066 , H01L2933/0075 , H01L2924/00014
Abstract: PURPOSE: A substrate for a semiconductor device, a semiconductor device having the substrate and a method for manufacturing the semiconductor device are provided to form the uniform thickness of a dielectric layer by using an anode oxidation method for forming an insulating layer. CONSTITUTION: A first metal line part(140) is electrically connected to a first electrode of a semiconductor device. A second metal line part(150) is electrically connected to a second electrode of the semiconductor device. A metal support part is arranged between the first metal line part and the second metal line part. A first insulation part(120) electrically insulates the first metal line part and the metal support part. A second insulation part(130) electrically insulates the second metal line part and the metal support part.
Abstract translation: 目的：提供一种用于半导体器件的衬底，具有衬底的半导体器件和用于制造半导体器件的方法，以通过使用用于形成绝缘层的阳极氧化法形成电介质层的均匀厚度。 构成：第一金属线部分（140）电连接到半导体器件的第一电极。 第二金属线部分（150）电连接到半导体器件的第二电极。 在第一金属线部分和第二金属线部分之间布置金属支撑部分。 第一绝缘部件（120）使第一金属线部分和金属支撑部分电绝缘。 第二绝缘部件（130）使第二金属线部分和金属支撑部分电绝缘。
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公开(公告)号：KR101185690B1
公开(公告)日：2012-09-24
申请号：KR1020110076821
申请日：2011-08-02
Applicant: 성균관대학교산학협력단
CPC classification number: H01L2924/0002 , H01L2924/00
Abstract: PURPOSE: A substrate processing method is provided to improve the planarity and height of through wires by performing a planarization process using a jig substrate having a plurality of receiving parts. CONSTITUTION: A first photo resist pattern and a second photoresist pattern(112) are formed on a substrate(100). A through wires(122) is formed by filling a through hole with conductive materials. A seed layer(120) is formed on an inner side of the through hole. A jig substrate(130) comprises a receiving part(132) corresponding to the through wire. A plurality of vacuum holes(134) is formed on the jig substrate in order to absorb the substrate.
Abstract translation: 目的：提供一种基板处理方法，通过使用具有多个接收部件的夹具基板进行平坦化处理来提高通孔的平面度和高度。 构成：在基板（100）上形成第一光刻胶图案和第二光刻胶图案（112）。 通过用导电材料填充通孔来形成通孔（122）。 种子层（120）形成在通孔的内侧。 夹具基板（130）包括对应于通孔的接收部分（132）。 为了吸收基板，在夹具基板上形成多个真空孔（134）。
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公开(公告)号：KR101184594B1
公开(公告)日：2012-09-21
申请号：KR1020100033554
申请日：2010-04-12
Applicant: 성균관대학교산학협력단
Abstract: 본 발명은 알루미늄 호일 상에 자기조립 단분자층으로 형성된 에칭터널 패턴을 형성한 후, 상기 에칭터널 패턴 이외의 부분에 산화물 마스크를 형성하고 전해에칭함으로써 알루미늄 호일 상에 에칭터널을 형성하는 것을 특징으로 하는 전해콘덴서용 알루미늄 전극의 제조방법에 관한 것이다. 본 발명에 따른 전해콘덴서용 알루미늄 전극은 에칭터널 형성시 산화물 마스크에 의해 에칭용액에 의한 알루미늄 부식이 억제되어 제조됨으로써 알루미늄 상부의 표면적이 유실되는 것이 방지되어 전해콘덴서의 내전압 및 파괴전압에 대한 신뢰성과 정전용량이 향상될 수 있다.
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公开(公告)号：KR101179386B1
公开(公告)日：2012-09-03
申请号：KR1020100032244
申请日：2010-04-08
Applicant: 삼성전기주식회사 , 성균관대학교산학협력단
CPC classification number: H01L21/50 , H01L23/13 , H01L23/147 , H01L23/49827 , H01L24/13 , H01L24/16 , H01L2224/131 , H01L2224/16146 , H01L2224/16235 , H01L2924/0001 , H01L2924/01006 , H01L2924/01019 , H01L2924/01023 , H01L2924/01033 , H01L2924/01078 , H01L2924/01082 , H01L2924/014 , H01L2924/19015 , H01L2924/19041 , Y10T436/170769 , H01L2224/13099
Abstract: There are provided a package substrate and a method fabricating thereof. The package substrate includes: a wafer having a cavity formed in an upper surface thereof, the cavity including a chip mounting region; a first wiring layer and a second wiring layer formed to be spaced apart from the first wiring layer, which are formed to be extended in the cavity; a chip positioned in the chip mounting region to be connected to the first wiring layer and the second wiring layer; a through-hole penetrating through the wafer and a via filled in the through-hole; and at least one electronic device connected to the via. Accordingly, a package substrate capable of having a passive device having a predetermined capacity embedded therein, while reducing a pattern size and increasing a component mounting density, and a method fabricating thereof may be provided.
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Patent Agency Ranking
公开(公告)号：KR101132574B1
公开(公告)日：2012-04-05
申请号：KR1020100068847
申请日：2010-07-16
Applicant: 성균관대학교산학협력단
Abstract: PURPOSE: A probe unit and a manufacturing method thereof are provided to prevent misalignment due to a bonding process and an alignment process between metal patterns. CONSTITUTION: A metal pattern is formed on one side of a substrate(110) and is filled with metal paste. The metal pattern is connected to the substrate in a connection penetration unit. A protection film(140) is coated on the upper side of the metal pattern and is comprised of insulation materials. A PCB(160) is attached to the upper side of the metal pattern and is connected to a measurement instrument. A probe unit(150) is connected to the metal paste.
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公开(公告)号：KR1020120010528A
公开(公告)日：2012-02-03
申请号：KR1020100072120
申请日：2010-07-26
Applicant: 성균관대학교산학협력단
IPC: H01L21/60
CPC classification number: H01L2224/11 , H01L2924/00012
Abstract: PURPOSE: A preparation method of a lead free solder bump using a sacrificial layer is provided to improve the mechanical reliability of a free lead solder bump which is formed finally by suppressing the growth of an inter metallic compound in the interface of copper post and a tin-based solder. CONSTITUTION: In a preparation method of a lead free solder bump using a sacrificial layer, a copper post(110) is formed on a substrate(100). A sacrificial layer(130) is formed on the copper post. The sacrificial layer is formed with a metal which is selected from palladium and a group which is formed with gold and platinum. A reflow process is performed after forming solder in the sacrificial layer. The solder is formed with a binary composite and or a ternary composite through electrolytic plating.
Abstract translation: 目的：提供一种使用牺牲层的无铅焊料凸块的制备方法，以提高自由铅焊料凸块的机械可靠性，最终通过抑制铜柱和锡的界面中的金属间化合物的生长而形成 的焊料。 构成：在使用牺牲层的无铅焊料凸块的制备方法中，在基板（100）上形成铜柱（110）。 牺牲层（130）形成在铜柱上。 牺牲层由选自钯和由金和铂形成的基团的金属形成。 在牺牲层中形成焊料之后进行回流工艺。 焊料通过电解电镀形成二元复合材料和/或三元复合材料。
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公开(公告)号：KR1020110129092A
公开(公告)日：2011-12-01
申请号：KR1020100048526
申请日：2010-05-25
Applicant: 성균관대학교산학협력단
Abstract: PURPOSE: A manufacturing method of a passive component embedded substrate is provided to manufacture an electronic product of an excellent structure with high reliability, thereby extending a lifespan of the electronic product and making a slimmer finished product. CONSTITUTION: A penetration hole(20) for embedding a passive component is arranged in a substrate. A via hole(10) for wiring is arranged in the substrate. The via hole for wiring is plated. A support stand is attached in one surface of the substrate. The passive component is embedded through the penetration hole. The wiring is arranged by plating the penetration hole for embedding the passive component.
Abstract translation: 目的：提供一种无源部件嵌入式基板的制造方法，以制造具有高可靠性的优异结构的电子产品，从而延长电子产品的寿命并制成更细的成品。 构成：用于嵌入无源部件的贯通孔（20）布置在基板中。 用于布线的通孔（10）设置在基板中。 接线用通孔进行电镀。 在基板的一个表面上附着支撑台。 被动部件通过穿透孔嵌入。 布线通过电镀用于嵌入被动元件的穿透孔而布置。
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公开(公告)号：KR1020110127513A
公开(公告)日：2011-11-25
申请号：KR1020100047043
申请日：2010-05-19
Applicant: 성균관대학교산학협력단
IPC: H01L23/488
CPC classification number: H01L2224/10
Abstract: PURPOSE: A method for manufacturing a silicon interposer is provided to easily form a solder bump by overcharging copper in the TSV(Through Silicon Via) of a substrate and projecting a copper post more than the substrate. CONSTITUTION: A TSV(Through Silicon Via)(130) is formed in a silicon substrate. An oxide film(140) and a copper seed layer(150) are formed in the silicon substrate in which the TSV is formed. A mask layer is formed in the upper side and the lower side of the silicon substrate. A copper post is formed to be dented more than a mask layer. One end of the cooper post is projected more than the silicon substrate by filling the copper in the TSV. Solder is deposited in one end of the copper post and the mask layer is removed. A solder bump is formed in one end of the copper post through a reflow process.
Abstract translation: 目的：提供一种用于制造硅插入件的方法，以便通过在基板的TSV（通过硅通孔）中对铜进行过充电而容易地形成焊料凸块，并将铜柱突出于基板以上。 构成：在硅衬底中形成TSV（硅通孔）（130）。 在形成TSV的硅衬底中形成氧化膜（140）和铜籽晶层（150）。 在硅衬底的上侧和下侧形成掩模层。 铜柱形成为比掩模层更凹陷。 通过在TSV中填充铜，铜柱的一端比硅衬底更突出。 在铜柱的一端沉积焊料，去除掩模层。 通过回流工艺在铜柱的一端形成焊料凸块。
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公开(公告)号：KR1020110114108A
公开(公告)日：2011-10-19
申请号：KR1020100033554
申请日：2010-04-12
Applicant: 성균관대학교산학협력단
Abstract: 본 발명은 알루미늄 호일 상에 자기조립 단분자층으로 형성된 에칭터널 패턴을 형성한 후, 상기 에칭터널 패턴 이외의 부분에 산화물 마스크를 형성하고 전해에칭함으로써 알루미늄 호일 상에 에칭터널을 형성하는 것을 특징으로 하는 전해콘덴서용 알루미늄 전극의 제조방법에 관한 것이다. 본 발명에 따른 전해콘덴서용 알루미늄 전극은 에칭터널 형성시 산화물 마스크에 의해 에칭용액에 의한 알루미늄 부식이 억제되어 제조됨으로써 알루미늄 상부의 표면적이 유실되는 것이 방지되어 전해콘덴서의 내전압 및 파괴전압에 대한 신뢰성과 정전용량이 향상될 수 있다.
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