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    Basic block cache microprocessor with instruction history information and method of execution and system thereof.
    31.
    发明专利
    Basic block cache microprocessor with instruction history information and method of execution and system thereof. 未知

    公开(公告)号：HK1035592A1

    公开(公告)日：2001-11-30

    申请号：HK01106104

    申请日：2001-08-29

    Applicant: IBM

    Inventor： KAHLE JAMES ALLAN

    IPC: G06F9/38 ,  G06F20060101 ,  G06F9/00 ,  G06F9/30 ,  G06F9/318 ,  G06F12/08 ,  G06F

    Abstract: A processor, data processing system, and a related method of execution are disclosed. The processor is suitable for receiving a set of instructions and organizing the set of instructions into an instruction group. The instruction group is then dispatched for execution. Upon executing the instruction group, instruction history information indicative of an exception event associated with the instruction group is recorded. Thereafter, the execution of the instruction is modified responsive to the instruction history information to prevent the exception event from occurring during a subsequent execution of the instruction group. The processor includes a storage facility such as an instruction cache, an L2 cache or a system memory, a cracking unit, and a basic block cache. The cracking unit is configured to receive a set of instructions from the storage facility. The cracking unit is adapted to organize the set of instructions into an instruction group.

    Concurrently executing multiple threads containing data dependent instructions
    35.
    发明专利
    Concurrently executing multiple threads containing data dependent instructions 未知

    公开(公告)号：GB2321544A

    公开(公告)日：1998-07-29

    申请号：GB9724351

    申请日：1997-11-19

    Applicant: IBM

    Inventor： KAHLE JAMES ALLAN ,  MALLICK SOUMMYA ,  MCDONALD ROBERT G

    IPC: G06F9/38 ,  G06F9/46 ,  G06F9/48

    Abstract: A processor and method of concurrently executing multiple threads are provided. The processor includes at least one register and an associated memory. According to the method, an execution control facility having first and second states is set to the first state. Execution of first and second threads is initiated such that the first and second threads are executed concurrently. Within the first thread, a first instruction is executed that stores to the associated memory a value that is referenced by a second instruction within the second thread. Thereafter, the execution control facility is set to the second state. Execution of the second instruction is permitted in response to the execution control facility being set to the second state. In another embodiment, the execution control facility is utilized to synchronize execution of multiple instructions within a second thread with execution of an instruction within a first thread.

    METHOD AND SYSTEM FOR INCREASED SYSTEM MEMORY CONCURRENCY IN A MULTIPROCESSOR COMPUTER SYSTEM
    36.
    发明专利
    METHOD AND SYSTEM FOR INCREASED SYSTEM MEMORY CONCURRENCY IN A MULTIPROCESSOR COMPUTER SYSTEM 未知

    公开(公告)号：CA2107056C

    公开(公告)日：1998-06-23

    申请号：CA2107056

    申请日：1993-09-27

    Applicant: IBM

    Inventor： OEHLER RICHARD RAPHAEL ,  KAHLE JAMES ALLAN ,  MUHICH JOHN STEPHEN ,  SILHA EDWARD JOHN

    IPC: G06F15/16 ,  G06F12/10 ,  G06F15/177

    Abstract: A method and system are disclosed for increasing memory concurrency in a multiprocessor computer system which includes system memory, multiple processors coupled together via a bus, each of the processors including multiple processor units for executing multiple instructions and for performing read, write and store operations and an associated Translation Lookaside Buffer (TLB) for translating effective addresses into real memory addresses within the system memory. Multiple page table entries are provided within a page table within the system memory which each include multiple individually accessible fields, an effective address and an associated real memory address for a selected system memory location. A reference bit is provided within a first individually accessible 5 in associated system memory location has been accessed for a read or write operation. A change bit is provided within a second individually accessible field within each page table entry and this change bit is utilized to indicate if an associated system memory location has been modified by a write operation. By storing the reference bit and change bit in separate including accessible fields the reference bit and change bit may be concurrently updated by multiple processors, increasing memory concurrency.

    CONVERTING SHORT BRANCHES TO PREDICATED INSTRUCTIONS
    40.
    发明专利
    CONVERTING SHORT BRANCHES TO PREDICATED INSTRUCTIONS 未知

    公开(公告)号：CA2356805A1

    公开(公告)日：2003-03-07

    申请号：CA2356805

    申请日：2001-09-07

    Applicant: IBM

    Inventor： MOORE CHARLES ROBERTS ,  KAHLE JAMES ALLAN

    IPC: G06F9/30 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38 ,  G06F15/76

    Abstract: A microprocessor and method of processing instructions therein are disclosed . Initially, a sequence of instructions is dispatched by a dispatch unit of the microprocessor. A code sequence recognition unit (CSR) is configured to detect a short branch sequence withi n the sequence of instruction, where the short branch sequence includes a condition setting instruction, a conditional branch, and at least one additional instruction that is executed if the conditional branch is not taken. The short branch sequence is then internally converted to a predicated instruction sequence that includes the condition setting instruction and a predicated instruction corresponding to each additional instruction in the short branch sequence. The predicated instruction sequence is then executed in at least one functional unit of the processor. Detecting the sho rt branch sequence may include calculating the relative branch address associated with the conditional branch instruction and comparing the relative branch address to a specified maximum. In one embodiment, the received sequence of instructions may be converted into an instruction group by the processor. In this embodiment, the specified maximum number of instructions in a short branch sequence may be a function of the number of instructions in an instructiongroup. In an embodiment where the conditional branch statement is preferably allocated to the last slot of the instruction group, the additional instructions in the short branch sequence are located in the next subsequent instruction group. Converting the short branch sequence to the predicated instruction sequence may include converting each additional instruction in the short branch sequence to an analogous predicated instruction. In one embodiment, converting each additional instruction to it s analogous predicated instruction includes determining a predicated instruction opcode for each additional instruction in the short branch sequence by adjusting the opcode of each additional instruction by a predetermined offset. In another embodiment, the opcode conversion may be accomplished wit h an opcode lookup table.

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