公开(公告)号：DE19931125A1

公开(公告)日：2001-01-25

申请号：DE19931125

申请日：1999-07-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HANEDER THOMAS ,  BACHHOFER HARALD ,  BRAUN GEORG

IPC: H01L21/28 ,  H01L29/51 ,  H01L29/78 ,  H01L27/105

Abstract: The invention relates to a ferroelectric transistor which has two source/drain areas (13) and a channel area between them, in a semiconductor substrate (11), and in which a first dielectric intermediate layer (14) is situated on the surface of the channel area. Above said first dielectric intermediate layer (14) are a ferroelectric layer (15), a second dielectric intermediate layer (16) and a gate electrode (17). The second dielectric intermediate layer (16) reduces the leakage currents through the ferroelectric layer (15) to the interface between the first dielectric layer (14) and the ferroelectric layer, hereby improving the data management.

公开(公告)号：DE102005033254A1

公开(公告)日：2007-01-25

申请号：DE102005033254

申请日：2005-07-15

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LEHMANN VOLKER ,  BINDER FLORIAN ,  HANEDER THOMAS ,  MARTIN ALFRED

IPC: H01L21/48 ,  H01L21/60 ,  H01L23/498

Abstract: The method involves producing blind holes and isolating layer in a front side upper surface (11) of a substrate (10), and isotropically etching a rear side upper surface by exposing the holes so that walls of the hole are formed. The holes are filled with metal or alloy by introducing the substrate into a melted mass process chamber under pressure. An independent claim is also included for a substrate filled with metal or metal alloy. The mass in the holes of the front surface are asymmetrically cooled so that contraction of the metal or alloy takes place, when cooling the holes in the rear surface till the solidified metal front surface lies at a level with the rear surface.

公开(公告)号：DE10142691B4

公开(公告)日：2006-04-20

申请号：DE10142691

申请日：2001-08-31

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HANEDER THOMAS ,  MARTIN ALFRED ,  LEHMANN VOLKER ,  EHBEN THOMAS ,  HANKE HANS CHRISTIAN ,  FUCHS KARIN

IPC: G01N33/50 ,  B01J19/00 ,  B01L3/00 ,  C12M1/34 ,  C12Q1/68 ,  C40B40/06 ,  C40B40/10 ,  C40B40/12 ,  C40B60/14 ,  G01N33/543 ,  G01N33/68

Abstract: A method for detecting a biochemical reaction includes immobilizing a capture molecule on an inner wall of a pore selected from a multiplicity of pores extending between first and second opposed surfaces of a macroporous substrate and contacting an analyte with the capture molecule. A light is then directed into the pore. A change in a light transmission property of the pore is then detected. This change indicates a binding reaction between the analyte and the capture molecule.

公开(公告)号：DE102004031167A1

公开(公告)日：2006-01-12

申请号：DE102004031167

申请日：2004-06-28

Applicant: INFINEON TECHNOLOGIES AG

Inventor： MARTIN ALFRED ,  DERTINGER STEPHAN ,  HANEDER THOMAS

IPC: B01J19/00 ,  C12Q1/68

公开(公告)号：DE10212878A1

公开(公告)日：2003-10-16

申请号：DE10212878

申请日：2002-03-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHMID GUENTER ,  HALIK MARCUS ,  KLAUK HAGEN ,  DEHM CHRISTINE ,  HANEDER THOMAS ,  MIKOLAJICK THOMAS

IPC: G11C13/02 ,  H01L21/02 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/28 ,  H01L51/20 ,  H01L51/10

Abstract: Semiconductor circuit arrangement comprises a pair of complementary field effect transistor devices (T1, T2) each having a gate region, first and second source/drain regions (SD11, SD12, SD21, SD22), and a channel region provided between each source/drain region. The gate regions and especially their gate electrodes are electrically coupled together via a capacitor arrangement (C1, C2). Preferably organic semiconductor material is provided in each channel region in the field effect transistor devices. The organic semiconductor material is a p-conducting or n-conducting semiconductor material. The gate electrode arrangement of the gate regions is electrically insulated by insulating regions (I1, I2) from the source/drain regions and the channel regions.

公开(公告)号：DE10211901A1

公开(公告)日：2003-10-16

申请号：DE10211901

申请日：2002-03-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： THEWES ROLAND ,  HANEDER THOMAS ,  SCHMID GUENTER ,  KLAUK HAGEN

IPC: G01N27/414 ,  G01N33/543 ,  G01N33/50 ,  C12Q1/68 ,  G01N27/02 ,  G01N27/22 ,  G01N27/416

公开(公告)号：DE10064031A1

公开(公告)日：2002-07-18

申请号：DE10064031

申请日：2000-12-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ULLMANN MARC ,  HANEDER THOMAS ,  HOENIGSCHMID HEINZ ,  GOEBEL HOLGER ,  HOENLEIN WOLFGANG

IPC: G11C11/22 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L29/788 ,  H01L29/792

Abstract: The state is read out from the ferroelectric transistor or stored in the ferroelectric transistor. During the read-out or storage of the state, at least one further ferroelectric transistor in the memory matrix is driven in such a way that it is operated in its depletion region.

公开(公告)号：DE10004392A1

公开(公告)日：2001-08-16

申请号：DE10004392

申请日：2000-02-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： REISINGER HANS ,  STEINLESBERGER GERNOT ,  HANEDER THOMAS ,  BACHHOFER HARALD

IPC: H01L21/336 ,  H01L29/78 ,  H01L29/792 ,  H01L29/772

Abstract: A source/drain voltage is applied to the field effect transistor during injection of the charge carriers in the channel area of the field effect transistor with the purpose of achieving inhomogeneous distribution of the charge carrier in the channel area.

公开(公告)号：DE19931124C1

公开(公告)日：2001-02-15

申请号：DE19931124

申请日：1999-07-06

Applicant: INFINEON TECHNOLOGIES AG

Inventor： HANEDER THOMAS ,  BACHHOFER HARALD

IPC: G11C11/22 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11502 ,  H01L27/12 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

Abstract: A memory cell configuration includes, as a memory cell, a ferroelectric transistor having a first gate intermediate layer and a first gate electrode between source/drain regions at the surface of a semiconductor substrate. The first gate intermediate layer contains at least one ferroelectric layer. Beside the first gate intermediate layer, a second gate intermediate layer and a second gate electrode are disposed between the source/drain regions, the second gate intermediate layer containing a dielectric layer. The first gate electrode and the second gate electrode are connected to one another through a diode structure. Strip-type doped well regions are provided in the semiconductor substrate, which well regions run between the source/drain regions of the respective ferroelectric transistor.