公开(公告)号：DE102004004594A1

公开(公告)日：2004-09-09

申请号：DE102004004594

申请日：2004-01-29

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： MALIK RAJEEV ,  RAMACHANDRAN RAVIKUMAR ,  DIVAKARUNI RAMACHANDRA ,  GLUSCHENKOV OLEG ,  YAN HONGWEN ,  YANG HAINING

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/336

Abstract: A method of fabricating a semiconductor device having a gate stack structure that includes gate stack sidewall, the gate stack structure having one or more metal layers comprising a gate metalis provided. The gate metal is recessed away from the gate stack sidewall using a chemical etch. The gate metal of the gate stack structure is selectively oxidized to form a metal oxide that at least partly fills the recess.

公开(公告)号：DE10361272A1

公开(公告)日：2004-08-05

申请号：DE10361272

申请日：2003-12-24

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： CHIDAMBARRAO DURESETI ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK A ,  VAN ROIJEN RAYMOND

IPC: H01L21/8242

Abstract: A DRAM cell with a vertical transistor forms a buried strap outdiffusion with reduced lateral extent by shifting high temperature steps that affect the thermal budget before the initial buried strap diffusion. The gate conductor is formed in two steps, with poly sidewalls being put down above a sacrificial Trench top oxide to form a self-aligned poly-gate insulator structure before the formation of the LDD extension.

公开(公告)号：DE10334946A1

公开(公告)日：2004-03-18

申请号：DE10334946

申请日：2003-07-31

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： BEINTNER JOCHEN ,  CHUDZIK MICHAEL PATRICK ,  RAJARAO JAMMY ,  DIVAKARUNI RAMACHANDRA

IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108

Abstract: In a vertical-transistor DRAM cell, the problem of making a reliable electrical connection between the node of the deep trench capacitor and the lower electrode of the vertical transistor is solved by; depositing a temporary insulator layer, forming a vertical spacer on the trench walls above the temporary insulator, then stripping the insulator to expose the substrate walls; diffusing dopant into the substrate walls to form a self-aligned extension of the buried strap; depositing the final gate insulator; and then forming the upper portion of the DRAM cell.

公开(公告)号：MY134452A

公开(公告)日：2007-12-31

申请号：MYPI20054051

申请日：2001-05-23

Applicant: IBM

Inventor： BERTIN CLAUDE L ,  DIVAKARUNI RAMACHANDRA ,  HOUGHTON RUSSELL J ,  MANDELMAN JACK A ,  TONTI WILLIAM R

IPC: H01L21/336 ,  H01L21/82 ,  H01L21/00 ,  H01L21/334 ,  H01L23/525 ,  H01L27/108 ,  H01L27/12

Abstract: AN ANTI-FUSE STRUCTURE THAT CAN BE PROGRAMMED AT LOW VOLTAGE AND CURRENT AND WHICH POTENTIALLY CONSUMES VERY LITTLE CHIP SPACES AND CAN BE FORMED INTERSTITIALLY BETWEEN ELEMENTS SPACED BY A MINIMUM LITHOGRAPHIC FEATURE SIZE IS FORMED ON A COMPOSITE SUBSTRATE SUCH AS A SILICON-ONINSULATOR WAFER BY ETCHING A CONTACT THROUGH AN INSULATOR TO A SUPPORT SEMICONDUCTOR LAYER, PREFERABLY IN COMBINATION WITH FORMATION OF A CAPACITOR-LIKE STRUCTURE REACHING TO OR INTO THE SUPPORT LAYER. THE ANTI-FUSE MAY BE PROGRAMMED EITHER BY THE SELECTED LOCATION OF CONDUCTOR FORMATION AND/OR DAMAGING A DIELECTRIC OF THE CAPACITOR-LIKE STRUCTURE. AN INSULATING COLLAR (38, 90) IS USED TO SURROUND A PORTION OF EITHER THE CONDUCTOR (42, 100) OR THE CAPACITOR-LIKE STRUCTURE TO CONFINE DAMAGE TO THE DESIRED LOCATION.HEATING EFFECTS VOLTAGE AND NOISE DUE TO PROGRAMMING CURRENTS ARE EFFECTIVELY ISOLATED TO THE BULK SILICON LAYER, PERMITTING PROGRAMMING DURING NORMAL OPERATION OF THE DEVICE. THUS THE POTENTIAL FOR SELF-REPAIR WITHOUT INTERRUPTION OF OPERATION IS REALIZED.(FIG 6)

公开(公告)号：DE10344862B4

公开(公告)日：2007-12-20

申请号：DE10344862

申请日：2003-09-26

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  FEHLAUER GERD T ,  KUDELKA STEPHAN ,  MANDELMAN JACK A ,  SCHROEDER UWE ,  TEWS HELMUT

IPC: H01L27/108 ,  H01L21/334 ,  H01L21/8242 ,  H01L29/94

Abstract: A trench capacitor memory cell structure is provided with includes a vertical collar region that suppresses current leakage of an adjacent vertical parasitic transistor that exists between the vertical MOSFET and the underlying trench capacitor. The vertical collar isolation, which has a vertical length of about 0.50 mum or less, includes a first portion that is present partially outside the trench and a second portion that is present inside the trench. The first portion of the collar oxide is thicker than said second portion oxide thereby reducing parasitic current leakage.

公开(公告)号：DE10324491A1

公开(公告)日：2004-01-08

申请号：DE10324491

申请日：2003-05-30

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  MALIK RAIEEV ,  RENGARAJAN RAIESH

IPC: H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/94

Abstract: Dual work function transistors are provided in a cmos support area 14 with an embedded vertical dram array 12. A wordline layer 54, and nitride cap layer 56 cover the dram array 12 and a gate oxide layer 42 and an undoped polysilicon layer 44 cover the support area 14. A common mask is applied and patterned over the substrate to define the wordlines line structures in the dram array 12 and the gate structures in the support 14. The unwanted portions of the layers 54, 56, 42 and 44 are removed by etching.

公开(公告)号：AU2002306174A1

公开(公告)日：2003-12-31

申请号：AU2002306174

申请日：2002-06-14

Applicant: IBM

Inventor： DIVAKARUNI RAMACHANDRA ,  GLUSCHENKOV OLEG ,  MANDELMAN JACK A ,  RADENS CARL J ,  WONG ROBERT C

IPC: H01L29/41 ,  H01L21/3205 ,  H01L21/74 ,  H01L21/76 ,  H01L21/762 ,  H01L21/768 ,  H01L21/82 ,  H01L21/8234 ,  H01L21/84 ,  H01L23/52 ,  H01L23/535 ,  H01L27/08 ,  H01L27/088 ,  H01L27/12 ,  H01L29/40 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786

Abstract: A structure and method is disclosed for forming a buried interconnect (10) of an integrated circuit in a single crystal semiconductor layer (12) of a substrate. The buried interconnect is formed of a deposited conductor and has one or more vertical sidewalls (18) which contact a single crystal region of an electronic device (20) formed in the single crystal semiconductor layer.

公开(公告)号：GB2497849A

公开(公告)日：2013-06-26

申请号：GB201222136

申请日：2012-12-10

Applicant: IBM

Inventor： YAMASHITA TENKO ,  DIVAKARUNI RAMACHANDRA ,  BU HUIMING ,  SHANG HUILING ,  CHUNG-HSUN LIN ,  ANDO TAKASHI ,  DORIS BRUCE B

IPC: H01L29/66 ,  H01L29/78

Abstract: A method to fabricate a field effect transistor includes forming on a surface of a semiconductor 10 a dummy gate structure comprised of a plug 14, forming a first spacer 18 surrounding the plug, the first spacer being a sacrificial spacer, and performing an angled ion implant so as to implant a dopant species into the surface of the semiconductor adjacent to an outer sidewall of the first spacer to form source and drain extension regions 20, such that the implanted species extends under the outer sidewall of the first spacer by an amount that is a function of the angle of the ion implant. The method further includes performing a laser anneal to activate the source and drain extension implants. In further processing, a second spacer is formed surrounding the first spacer, the first spacer and dummy gate are removed to form an opening and a gate stack is deposited in the opening.

公开(公告)号：DE60129605T2

公开(公告)日：2008-06-05

申请号：DE60129605

申请日：2001-11-28

Applicant: IBM ,  QIMONDA NORTH AMERICA CORP

Inventor： GRUENING ULRIKE ,  DIVAKARUNI RAMACHANDRA ,  MANDELMAN JACK ,  RUPP THOMAS

IPC: H01L21/00 ,  H01L27/10 ,  H01L21/8242

Abstract: A process for producing very high-density embedded DRAM/very high-performance logic structures comprising fabricating vertical MOSFET DRAM cells with salicided source/drain and gate conductor dual workfunction MOSFETs in the supports.

公开(公告)号：DE102004060891A1

公开(公告)日：2005-08-11

申请号：DE102004060891

申请日：2004-12-17

Applicant: IBM ,  INFINEON TECHNOLOGIES AG

Inventor： RADENS CARL ,  DYER THOMAS W ,  SUNG CHUN-YUNG ,  DIVAKARUNI RAMACHANDRA ,  RAMACHANDRAN RAVIKUMAR

IPC: H01L21/8242 ,  H01L29/94 ,  H01L27/108