公开(公告)号：JPH11145415A

公开(公告)日：1999-05-28

申请号：JP24707098

申请日：1998-09-01

Applicant: SIEMENS AG ,  IBM

Inventor： HAMMERL ERWIN ,  MANDELMAN JACK A ,  SHORT ALVIN P ,  STENGL REINHARD J ,  HO HERBERT L ,  POSCHENRIEDER BERNHARD ,  SRINIVASAN RADHIKA

IPC: H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a second device of a transistor, for example, on first device of a trench, for example, in the manufacture of a dynamic random access memory using a three-dimensional trench capacitor. SOLUTION: A layer having an uppermost face of a single crystal is formed on a first device, and a layer 2 is used as a base for forming an active region of a second device. In this case, a substrate 305 having a single-crystal structure and the flat substrate surface is prepared, and a trench capacitor 315 is manufacture in the substrate. A polysilicon layer in the capacitor 315 is bored in the part lower than the substrate surface to form a recessed part, and an intermediate layer is formed in the recessed part to a height larger than the surface of a pad. This intermediate layer has the uppermost face of the single crystal. The surface of the intermediate layer and the pad are planarized in such a way that the uppermost surface of the intermediate layer substantially becomes flat to the substrate surface and a transistor 370 is manufactured on the uppermost face of the single crystal.

公开(公告)号：JP2004214627A

公开(公告)日：2004-07-29

申请号：JP2003396333

申请日：2003-11-26

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DORIS BRUCE B ,  DOKUMACI OMER H ,  MANDELMAN JACK A ,  RADENS CARL J

IPC: H01L21/265 ,  H01L21/28 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786

CPC classification number: H01L21/28114 ,  H01L21/26586 ,  H01L21/82385 ,  H01L21/823864 ,  H01L29/42376 ,  H01L29/665

Abstract: PROBLEM TO BE SOLVED: To provide an FET device in which the gate activity, line resistance and S/D extension resistance are improved. SOLUTION: A method for manufacturing a semiconductor transistor device is provided with following steps: a semiconductor substrate is formed; the semiconductor substrate has a gate dielectric layer on its surface; lower gate electrode structure is formed on the surface of the gate dielectric layer and the lower gate electrode structure has a low gate upper surface; a planarized layer is formed on the gate dielectric layer so that the upper part of the lower gate electrode structure is left in an exposed state; upper gate structure is formed on the lower gate electrode structure to form a T-type gate electrode; the lower surface of the upper gate structure and the vertical sidewall of the gate electrode are exposed; the planarized layer is removed; a source/drain extension is formed in the substrate protected from a short channel effect; a sidewall spacer is formed adjacent to the exposed lower surface of the upper gate and the exposed vertical sidewall of the T-type gate electrode. A source/drain region is formed in the substrate. A silicide layer is formed on the upper part of the T-type gate electrode and the upper part of the source/drain region. COPYRIGHT: (C)2004,JPO&NCIPI

公开(公告)号：JP2002124672A

公开(公告)日：2002-04-26

申请号：JP2001193470

申请日：2001-06-26

Applicant: IBM

Inventor： CLEVENGER LAWRENCE ALFRED ,  MANDELMAN JACK A ,  JAMMY RAJARO ,  GLUSCHENKOV OLEG ,  MCSTAY IRENE LENNOX ,  WONG KWONG HON ,  FALTERMEIER JONATHAN

IPC: H01L29/43 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a gate structure for MOSFETs for application of the CMOS technology, etc., which is durable against high temperature processes such as junction activation, etc., and reduces the gate propagation delay. SOLUTION: The gate structure 10 has an insulation layer 14 on a semiconductor substrate 12, and a polysilicon gate electrode 16 on the insulation layer 14. The gate structure 10 comprises a diffused barrier layer 20 having semi- insulative characteristics on the gate electrode 16, and a gate conductor 18 on the barrier layer 20. The conductor 18 is electrically contacted to the gate electrode 16. The constitution and the thickness of the barrier layer 20 are adjusted so as to effectively block the diffusion and the mixing between the gate conductor 18 and the gate electrode 16, but realize a capacitive coupling and/or a leak current not so increasing the gate propagation delayer of the gate surface 10.

公开(公告)号：JP2002026148A

公开(公告)日：2002-01-25

申请号：JP2001189096

申请日：2001-06-22

Applicant: IBM

Inventor： MANDELMAN JACK A ,  DIVAKARUNI RAMACHANDRA ,  RADENS CARL J ,  GRUENING ULRIKE ,  SUDO AKIRA

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To provide a new deep trench(DT) collar process which reduces disturbance of strap diffusion to an array metal oxide semiconductor field effect transistor(MOSFET) of a semiconductor device. SOLUTION: By this method, an oxidation barrier layer is formed on a sidewall of the DT provided in the semiconductor substrate, a photoresist layer of specific depth is provided in the trench to remove the oxidation barrier layer to specific depth and expose the trench sidewall, and the remaining photoresist is removed. A layer of a silicon material is stuck on the exposed trench sidewall, and a dielectric layer is formed on the silicon material layer to form a collar. The remaining oxidation barrier layer is removed from the trench and polysilicon which forms a storage node is charged. Consequently, the distance between a MOSFET gate and a DT storage capacitor is maximized, and the effective edge bias of the DT at its peak is reducible without spoiling the storage capacity.

公开(公告)号：JP2002026147A

公开(公告)日：2002-01-25

申请号：JP2001189079

申请日：2001-06-22

Applicant: IBM

Inventor： MANDELMAN JACK A ,  RAMACHANDORA DEIVAKARUNI ,  KAARU JIEI RADENSU ,  GRUENING ULRIKE

IPC: H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a memory cell structure including a planar semiconductor substrate. SOLUTION: The semiconductor substrate has a deep trench. The deep trench has side walls and one bottom part. A storage capacitor is located at the bottom of the deep trench. On at least one sidewall of the deep trench, a vertical transistor extends downwardly. This transistor has source diffusion extending in the plane of the substrate adjacent to the deep trench. On at least the other sidewall of the deep trench on the opposite side from the vertical transistor, a separation part extends downwardly. A shallow trench separation area extends laterally to the sidewall, where the vertical transistor extends along the surface of the substrate. In the inside of the deep trench, a gate conductor extends. A word line extends onto the deep trench and is connected to the gate conductor. The bit line extends onto the surface of the substrate and has a contact for the source diffusion between shallow trench separation areas.

公开(公告)号：JP2001060698A

公开(公告)日：2001-03-06

申请号：JP2000209836

申请日：2000-07-11

Applicant: IBM

Inventor： MICHAEL J HAAGUROVU ,  MANDELMAN JACK A

IPC: H01L21/28 ,  H01L21/768 ,  H01L23/522 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To form an SOI(silicon-on-insulator) structure substrate, having a body contact (a base-body contact) under a gate conductor. SOLUTION: A gate conductor on SOI semiconductor structure is partitioned into segments, and the body contact is formed under the gate conductor segment. The body contact is formed by an opening. The opening is extended to a silicon substrate 22 through a TEOS layer 24, an SOI layer 18 and an oxide layer 20. A polysilicon layer 38, a TEOS layer 40 and a polysilicon layer 42 are formed at the opening. Charges stored from a body region under a gate can be removed rapidly by shaping the body contact, and a stable efficient SOI MOSFET can be realized.

公开(公告)号：JP2000058655A

公开(公告)日：2000-02-25

申请号：JP17440199

申请日：1999-06-21

Applicant: IBM

Inventor： ARNDT KENNETH C ,  GAMBINO JEFFREY P ,  MANDELMAN JACK A ,  NARAYAN CHANDRASEKHAR ,  SCHNABEL RAINER F ,  SCHUTZ RONALD J ,  TOEBBEN DIRK

IPC: H01L21/82 ,  H01L21/768 ,  H01L23/525

Abstract: PROBLEM TO BE SOLVED: To improve the control of thickness of an insulator layer on a fuse structure, by a method wherein a dielectric structure is positioned on a conduction level, and electric connection is performed at a selected position of the conduction level through the dielectric structure. SOLUTION: On a semiconductor substrate 10 an electric conduction level 1 is formed by using conductive material selected out of aluminum, copper, aluminum copper alloy, and doped polysilicon having metal type conductivity. A dielectric etching stop material layer 2 is stuck on the upper surface of the electric conduction level 1. Electric connection is performed to a selected position of the electric conduction level 1 through the dielectric etching stop material layer 2, and a conductive fuse 21 is constituted. As a result control of the thickness of an insulator layer on the fuse structure containing a self-aligned isolation cap can be improved.

公开(公告)号：JP2000022101A

公开(公告)日：2000-01-21

申请号：JP15133899

申请日：1999-05-31

Applicant: IBM ,  SIEMENS AG

Inventor： GAMBINO JEFFREY P ,  GRUENING ULRIKE ,  MANDELMAN JACK A ,  KAARU JIEI RADENSU

IPC: H01L27/108 ,  H01L21/8242

Abstract: PROBLEM TO BE SOLVED: To reduce remarkably the distributed series resistance of trench electrodes, by manufacturing trench capacitors using a method of forming heat- resistant metallic salicide materials on the trench regions having low trench capacitors. SOLUTION: A narrow upper region 16a and a wide lower region 16b are filled with ploysilicon layers 26 and the polysilicon layers 26 are planarized. Next, the polysilicon layers 26 are recessed, then conformal heat-resistant metallic layers 30 are adhered. After that, the salicide is formed at the interface between the heat-resistant metal in the region 16b and the polysilicon by annealing. As a result, a heat-resistant metallic salicide layer 32 is formed in the wide lower trench region 16b. It is preferable that the heat-resistant metallic salicide layer is not formed in the narrow upper trench region 16b. Next, the heat-resistant metallic layer 30 remained in the upper layer 16a is removed. Then, the additional polysilicon is filled in the trench. After that, the capacitor structure is planarized.

公开(公告)号：JPH11297812A

公开(公告)日：1999-10-29

申请号：JP34271998

申请日：1998-12-02

Applicant: IBM ,  TOSHIBA CORP

Inventor： MANDELMAN JACK A ,  MORIKADO MUTSUO ,  HO HERBERT ,  JEFFREY P GANBINO

IPC: H01L21/76 ,  H01L21/762

Abstract: PROBLEM TO BE SOLVED: To inhibit the formation of a recessed part and to prevent the large change of threshold voltage and off current, by previously removing a nitride liner on the upper part of a side wall with shallow trench element separation. SOLUTION: Resist 17 is etched to the depth of 1000 Å from the surface of a silicon substrate by chemical dry etching(CDE). A silicon nitride liner 16a at the upper part of a shallow trench 14 is removed and whole resist 17a in the shallow trench 14 is removed by CDE. TEOS oxide is embedded in the shallow trench 14, and shallow element separation is formed. A pad nitride film 13 and a pad oxide film 12 on a separated element area are removed, and a gate oxide film and a gate electrode are formed. A source area and a drain area are formed by ion implanting and MOSFET is completed. At the time of removing the pad nitride film 13, a recessed part by the removal of the silicon nitride liner is not formed since the silicon nitride liner is not exposed to a surface.

公开(公告)号：JPH11260935A

公开(公告)日：1999-09-24

申请号：JP4799

申请日：1999-01-04

Applicant: IBM

Inventor： BRONNER GARY BELA ,  GAMBINO JEFFREY P ,  MANDELMAN JACK A ,  RADENS CARL J ,  TONTI WILLIAM R

IPC: H01L21/225 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To manufacture a cap self-aligned on a gate conductor, and realize a two actional function for selectively applying P doping and N doping to the gate conductor. SOLUTION: A selected number of gate structures having self-aligned insulating layers 2 and 4 are doped by a first conductive type dopant through at least one sidewall of the gate structure. Thus, one gate structure is doped with the first conductive dopant, and another gate structure is doped with a second and different conductive dopant in this gate structural array. Therefore, a two actional function can be given.