公开(公告)号：US20160200566A1

公开(公告)日：2016-07-14

申请号：US14403571

申请日：2013-06-28

Applicant: INTEL IP CORPORATION

Inventor： Gerald Ofner ,  Thorsten Meyer ,  Reinhard Mahnkopf ,  Christian Geissler ,  Andreas Augustin

IPC: B81B7/00 ,  B81C1/00

CPC classification number: B81C1/00238 ,  B81B7/008 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/025 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2201/0271 ,  B81B2201/10 ,  B81B2207/012 ,  B81B2207/053 ,  B81B2207/07 ,  B81B2207/096 ,  B81C1/0023 ,  B81C2203/0792 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.

Abstract translation: 在实施例中，封装组件可以包括专用集成电路（ASIC）和具有有源侧和无源侧的微机电系统（MEMS）。 在实施例中，MEMS可以通过一个或多个互连直接耦合到ASIC。 MEMS，ASIC和一个或多个互连可以限定或形成空腔，使得MEMS的有源部分在空腔内。 在一些实施例中，封装组件可以包括通过多个一个或多个互连件直接耦合到ASIC的多个MEMS。 可以描述和/或要求保护其他实施例。

公开(公告)号：US10403609B2

公开(公告)日：2019-09-03

申请号：US15776475

申请日：2015-12-21

Applicant: Intel IP Corporation

Inventor： Christian Geissler ,  Sven Albers ,  Georg Seidemann ,  Andreas Wolter ,  Klaus Reingruber ,  Thomas Wagner ,  Marc Dittes

IPC: H01L23/02 ,  H01L25/16 ,  H01L23/48 ,  H01L25/065 ,  H01L25/07 ,  H01L23/00 ,  H01L23/498 ,  H01L23/538 ,  H01L21/56

Abstract: A system-in-package device includes at least three electrical device components arranged in a common package. A first electrical device component includes a first vertical dimension, a second electrical device component includes a second vertical dimension and a third electrical device component comprises a third vertical dimension. The first electrical device component and the second electrical device component are arranged side by side in the common package. Further, the third electrical device component is arranged on top of the first electrical device component in the common package. At least a part of the third electrical device component is arranged vertically between a front side level of the second electrical device component and a back side level of the second electrical device component.

公开(公告)号：US20180186627A1

公开(公告)日：2018-07-05

申请号：US15857461

申请日：2017-12-28

Applicant: Intel IP Corporation

Inventor： Gerald Ofner ,  Thorsten Meyer ,  Reinhard Mahnkopf ,  Christian Geissler ,  Andreas Augustin

IPC: B81C1/00 ,  B81B7/00

CPC classification number: B81C1/00238 ,  B81B7/008 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/025 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2201/0271 ,  B81B2201/10 ,  B81B2207/012 ,  B81B2207/053 ,  B81B2207/07 ,  B81B2207/096 ,  B81C1/0023 ,  B81C2203/0792 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.

公开(公告)号：US09663353B2

公开(公告)日：2017-05-30

申请号：US14403571

申请日：2013-06-28

Applicant: Intel IP Corporation

Inventor： Gerald Ofner ,  Thorsten Meyer ,  Reinhard Mahnkopf ,  Christian Geissler ,  Andreas Augustin

IPC: H01L27/14 ,  B81B7/00 ,  B81C1/00

CPC classification number: B81C1/00238 ,  B81B7/008 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/025 ,  B81B2201/0257 ,  B81B2201/0264 ,  B81B2201/0271 ,  B81B2201/10 ,  B81B2207/012 ,  B81B2207/053 ,  B81B2207/07 ,  B81B2207/096 ,  B81C1/0023 ,  B81C2203/0792 ,  H01L2224/16225 ,  H01L2224/48091 ,  H01L2924/15311 ,  H01L2924/00014

Abstract: In embodiments, a package assembly may include an application-specific integrated circuit (ASIC) and a microelectromechanical system (MEMS) having an active side and an inactive side. In embodiments, the MEMS may be coupled directly to the ASIC by way of one or more interconnects. The MEMS, ASIC, and one or more interconnects may define or form a cavity such that the active portion of the MEMS is within the cavity. In some embodiments, the package assembly may include a plurality of MEMS coupled directly to the ASIC by way of a plurality of one or more interconnects. Other embodiments may be described and/or claimed.

公开(公告)号：US09397019B2

公开(公告)日：2016-07-19

申请号：US14189938

申请日：2014-02-25

Applicant: INTEL IP CORPORATION

Inventor： Sven Albers ,  Sonja Koller ,  Thorsten Meyer ,  Georg Seidemann ,  Christian Geissler ,  Andreas Wolter

IPC: H01L23/02 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L21/56 ,  H01L21/568 ,  H01L21/78 ,  H01L23/3128 ,  H01L23/562 ,  H01L24/96 ,  H01L24/97 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/3511 ,  H01L2924/00

Abstract: Embodiments of the present disclosure are directed towards an integrated circuit (IC) package including a die having a first side and a second side disposed opposite to the first side. The IC package may further include an encapsulation material encapsulating at least a portion of the die and having a first surface that is adjacent to the first side of the die and a second surface disposed opposite to the first surface. In embodiments, the second surface may be shaped such that one or more cross-section areas of the IC package are thinner than one or more other cross-section areas of the IC package. Other embodiments may be described and/or claimed.

Abstract translation: 本公开的实施例涉及集成电路（IC）封装，其包括具有与第一侧相对设置的第一侧和第二侧的管芯。 IC封装还可以包括封装模具的至少一部分并且具有与模具的第一侧相邻的第一表面的封装材料和与第一表面相对设置的第二表面。 在实施例中，第二表面可以被成形为使得IC封装的一个或多个横截面积比IC封装的一个或多个其它横截面积更薄。 可以描述和/或要求保护其他实施例。