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    31.
    发明专利
    未知

    公开(公告)号：DE69819919D1

    公开(公告)日：2003-12-24

    申请号：DE69819919

    申请日：1998-12-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： DEMICHELI MARCO ,  BRUCCOLERI MELCHIORRE ,  MALFA MAURIZIO ,  BOLLATI GIACOMINO

    IPC: G11B5/09 ,  G11B5/012 ,  G11B20/10

    Abstract: A method of delaying by a certain time interval ( DELTA wp) a transition in a digital data stream (O) fed to a write head of a mass storage device when said transition occurs at a clock phase following the one during which a preceding transition has occurred, for pre-compensating intersymbolic nonlinear interference effects suffered when reading the stored data, comprises feeding to a first circuit (CC1) a digital data stream (I) to be stored and a clock signal (Ck) and outputting from said first circuit (CC1) a pair of digital streams (N, R), a first stream (N) assuming a first logic value every time a transition of said input stream occurs during a clock phase not successive to a clock phase during which a transition of said input stream (I) has occurred, the second stream (R) assuming said first logic value every time a transition of said input stream (I) occurs during a clock phase following a clock phase during which a transition has taken place in said input stream (I); feeding said two digital stream (N, R) and said clock signal (Ck) to as many inputs of a second circuit (DC1) and outputting from said second circuit said digital data stream (O) directed to the write head, in which the transitions immediately following a preceding transition are delayed by said pre-established time interval ( DELTA wp), by sampling the two digital streams (N, R) with a pair of flip-flops (FN2, FR2), each of which is respectively timed by clock signals respectively delayed by a certain different time interval ( DELTA n, DELTA r) and such that the difference between said different delay intervals is equal to said pre-established time interval ( DELTA n- DELTA r= DELTA wp) and recombining the signals output from said pair of flip-flops (FN2, FR2) through an logic XOR gate (X1) into said digital data stream (O).

    33.
    发明专利
    未知

    公开(公告)号：DE69624460D1

    公开(公告)日：2002-11-28

    申请号：DE69624460

    申请日：1996-01-26

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： ALINI ROBERTO ,  BRUCCOLERI MELCHIORRE ,  COSENTINO GAETANO ,  PISATI VALERIO

    IPC: H03F3/30 ,  H03F3/34 ,  H03F1/00

    Abstract: The amplifier described has an output stage constituted by an npn transistor (Q1) and a pnp transistor (Q2) in a push-pull arrangement, and a driver stage. The latter comprises a current-mirror circuit having, in its input branch, a pnp transistor (Q3) in series with a first constant-current generator (G1) and, in its output branch, an npn transistor (Q4), and two complementary transistors (Q5 and Q6) of which the collectors are connected together to the output terminal (OUT) and the bases are connected together to the input terminal (IN) of the amplifier. The emitter of the pnp transistor (Q5) of the driver stage is connected to the positive terminal (vdd) of the supply by means of a second constant-current generator (G2) and to the base of the npn transistor (Q1) of the output stage, and the emitter of the npn transistor (Q6) of the driver stage is connected to the negative terminal (gnd) of the supply by means of the npn transistor (Q4) of the output branch of the current-mirror circuit and to the base of the pnp transistor (Q2) of the output stage. The amplifier has a very low or zero offset (Vos = Vout-Vin).

    34.
    发明专利
    未知

    公开(公告)号：DE69520562D1

    公开(公告)日：2001-05-10

    申请号：DE69520562

    申请日：1995-05-15

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BRUCCOLERI MELCHIORRE ,  DEMICHELI MARCO ,  PATTI GIUSEPPE ,  PISATI VALERIO

    IPC: H03M1/68 ,  G06J1/00 ,  H03M1/66 ,  H03M1/78 ,  H03M1/00

    Abstract: A digital/analog quadratic converter (DACQ) composed by a pair of linear converters connected in cascade has a direct coupling of the output node of the first converter (DAC1) with a node of a R-2R type resistive network of the second converter (DAC2) corresponding to the LSB stage of the R-2R type resistive network. High impedance nodes, notably the input node of the second linear converter, are advantageously eliminated from the "current path" thus markedly reducing the problems of relatively long settling times of high impedance nodes (having intrinsically large parasitic capacitances associated therewith). The peculiar architecture of the quadratic converter provides also for a remarkable simplification of the circuit.

    35.
    发明专利
    未知

    公开(公告)号：DE69426776D1

    公开(公告)日：2001-04-05

    申请号：DE69426776

    申请日：1994-12-27

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： BRUCCOLERI MELCHIORRE ,  COSENTINO GAETANO ,  DEMICHELI MARCO ,  PORTALURI SALVATORE

    IPC: G06G7/16 ,  G06G7/163

    Abstract: The error on the output signal produced by an analog multiplier comprising at least a differential output stage formed by a pair of emitter-coupled bipolar transistors (Q3, Q4), each driven by a predistortion stage (Q1, Q2) having a reciprocal of a hyperbolic tangent transfer function, attributable to the base currents of the bipolar transistors used, is compensated by generating replicas of the base current of the bipolar transistors (Q3, Q4) of said differential stage and forcing said replica currents on the output node of the respective predistortion stage (Q1, Q2). Various embodiments of different dissipative behaviours are described.

    37.
    发明专利
    未知

    公开(公告)号：DE69519663D1

    公开(公告)日：2001-01-25

    申请号：DE69519663

    申请日：1995-03-07

    Applicant: ST MICROELECTRONICS SRL

    Inventor： BRUCCOLERI MELCHIORRE ,  VAI GIANFRANCO ,  PORTALURI SALVATORE ,  DEMICHELI MARCO

    IPC: H03L7/093 ,  H03L7/089 ,  H03L7/099 ,  H03L7/107

    Abstract: A fully integrated, phase locked loop (PLL) having improved jitter characteristics exploits the same digital/analog converter (DAC) that is normally used for controlling the time constant of the low pass loop filter for controlling the value of a capacitance connected between the output of a voltage-to-current converting input stage of the voltage controlled oscillator and ground that introduces a third pole in the loop's transfer function. In this way the separation in the frequency domain between the zero and the third pole of the transfer function is kept constant, thus the dumping factor remains constant while the omega o of the PLL is varied.

    38.
    发明专利
    未知

    公开(公告)号：DE69515869T2

    公开(公告)日：2000-12-07

    申请号：DE69515869

    申请日：1995-09-14

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： BRUCCOLERI MELCHIORRE ,  DEMICHELI DAVIDE ,  DEMICHELI MARCO ,  PATTI GIUSEPPE

    IPC: H03G3/30 ,  G11B5/02 ,  H03G1/00 ,  H03G3/20

    Abstract: The circuit described comprises a double half-wave rectifier (DHWR) connected to the outputs of the differential amplifier (VGA) in order to produce two quantities dependent on the amplitudes of the half-waves of the output signal of the amplifier (VGA), two comparators (COMP1, COMP2) each having an input (IN+1, IN+2) connected to an output (OUT1, OUT2) of the rectifier (DHWR) and a reference input (IN-1, IN-2) in order to produce respective output signals when the amplitudes of the respective half-waves are greater than the levels applied to the reference inputs (IN-1, IN-2), and processing means (Str1, A1, R1, Str2, A2, R2, C) for generating a signal for regulating the gain of the amplifier in dependence on the durations of the output signals of the two comparators. The circuit may advantageously be used when the signal to be amplified (v+, v-) is not symmetrical.

    40.
    发明专利
    未知

    公开(公告)号：DE69515869D1

    公开(公告)日：2000-04-27

    申请号：DE69515869

    申请日：1995-09-14

    Applicant: ST MICROELECTRONICS SRL ,  CONS RIC MICROELETTRONICA

    Inventor： BRUCCOLERI MELCHIORRE ,  DEMICHELI DAVIDE ,  DEMICHELI MARCO ,  PATTI GIUSEPPE

    IPC: H03G3/30 ,  G11B5/02 ,  H03G1/00 ,  H03G3/20

    Abstract: The circuit described comprises a double half-wave rectifier (DHWR) connected to the outputs of the differential amplifier (VGA) in order to produce two quantities dependent on the amplitudes of the half-waves of the output signal of the amplifier (VGA), two comparators (COMP1, COMP2) each having an input (IN+1, IN+2) connected to an output (OUT1, OUT2) of the rectifier (DHWR) and a reference input (IN-1, IN-2) in order to produce respective output signals when the amplitudes of the respective half-waves are greater than the levels applied to the reference inputs (IN-1, IN-2), and processing means (Str1, A1, R1, Str2, A2, R2, C) for generating a signal for regulating the gain of the amplifier in dependence on the durations of the output signals of the two comparators. The circuit may advantageously be used when the signal to be amplified (v+, v-) is not symmetrical.

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