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公开(公告)号：ITTO20000892D0
公开(公告)日：2000-09-22
申请号：ITTO20000892
申请日：2000-09-22
Applicant: ST MICROELECTRONICS SRL
Inventor： SACCO ANDREA , KHOURI OSAMA , TORELLI GUIDO , MICHELONI RINO
Abstract: Described herein is a nonvolatile memory comprising a memory array organized according to global word lines and local word lines; a global row decoder; a local row decoder; a first supply stage for supplying the global row decoder; and a second supply stage for supplying the local row decoder; and a third supply stage for biasing the drain and source terminals of the memory cells of the memory array. Each of the supply stages comprises a respective resistive divider formed by a plurality of series-connected resistors, and a plurality of pass-gate CMOS switches each connected in parallel to a respective resistor. The nonvolatile memory further comprises a control circuit for controlling the pass-gate CMOS switches of the supply stages, and a switching circuit for selectively connecting the supply input of the control circuit to the output of the second supply stage during reading and programming of the memory, and to the output of the third supply stage during erasing of the memory.
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公开(公告)号：ITMI20001585D0
公开(公告)日：2000-07-13
申请号：ITMI20001585
申请日：2000-07-13
Applicant: ST MICROELECTRONICS SRL
Inventor： KHOURI OSAMA , TORELLI GUIDO , MICHELONI RINO , PIERIN ANDREA , GREGORI STEFANO , SANGALLI MIRIAM
IPC: G11C16/08
Abstract: A circuit device for performing hierarchic row decoding in semiconductor memory devices of the non-volatile type, which memory devices include an array of memory cells with column-ordered sectors, wherein each sector has a respective group of local wordlines linked to a main wordline. The circuit device includes a main wordline driver provided at each main wordline, and a local decoder provided at each local wordline. This circuit device further comprises, for each main wordline, a dedicated path connected between the main wordline and the local decoders of the associated local wordlines and connected to an external terminal arranged to receive a read/program voltage, the dedicated path enabling transfer of the read/program voltage to the local decoders.
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公开(公告)号：DE69516402D1
公开(公告)日：2000-05-25
申请号：DE69516402
申请日：1995-07-31
Applicant: ST MICROELECTRONICS SRL
Inventor： CALLIGARO CRISTIANO , DANIELE VINCENZO , GASTALDI ROBERTO , MANSTRETTA ALESSANDRO , TELECCO NICOLA , TORELLI GUIDO
IPC: G11C11/56
Abstract: A method for sensing multiple-levels non-volatile memory cells which can take one programming level among a plurality of m=2 (n > = 2) different programming levels, provides for biasing a memory cell (MC) to be sensed in a predetermined condition, so that the memory cell (MC) sinks a cell current (IC) with a value belonging to a discrete set of m distinct cell current values (IC0-IC15), each cell current value (IC0-IC15) corresponding to one of said programming levels. The sensing method also provides for: simultaneously comparing the cell current (IC) with a prescribed number of reference currents (IR1,IR2,IR3) having values comprised between a minimum value and a maximum value of said discrete set of m cell current values (IC0-IC15) and dividing said discrete set of m cell current values (IC0-IC15) in a plurality of sub-sets of cell current values, for determining the sub-set of cell current values to which the cell current (IC) belongs; repeating step a) for the sub-set of cell current values to which the cell current (IC) belongs, until the sub-set of cell current values to which the cell current (IC) belongs comprises only one cell current value, which is the value of the current (IC) of the memory cell (MC) to be sensed.
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公开(公告)号：DE69514783D1
公开(公告)日：2000-03-02
申请号：DE69514783
申请日：1995-03-23
Applicant: ST MICROELECTRONICS SRL
Inventor： CALLIGARO CRISTIANO , DANIELE VINCENZO , GASTALDI ROBERTO , MANSTRETTA ALESSANDRO , TELECCO NICOLA , TORELLI GUIDO
Abstract: A sensing circuit for serial dichotomic sensing of multiple-levels memory cells (MC) which can take one programming level among a plurality of m=2 (n >= 2) different programming levels, comprises biasing means for biasing a memory cell (MC) to be sensed in a predetermined condition, so that the memory cell (MC) sinks a cell current (IC) with a value belonging to a plurality of m distinct cell current values (IC0-IC3), each cell current value (IC0-IC3) corresponding to one of the programming levels, a current comparator (1) for comparing the cell current (IC) with a reference current (IR) generated by a variable reference current generator (G), and a successive approximation register (2) supplied with an output signal (CMP) of the current comparator (1) and controlling the variable reference current generator (G). The variable reference current generator comprises an offset current generator (Ioff) permanently coupled to the current comparator (1), and m-2 distinct current generators (IR0,IR1), independently activatable by the successive approximation register (2), each one generating a current (IC1,IC2) equal to a respective one of the plurality of cell current values (IC0-IC3).
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公开(公告)号：ITTO990993D0
公开(公告)日：1999-11-16
申请号：ITTO990993
申请日：1999-11-16
Applicant: ST MICROELECTRONICS SRL
Inventor： KHOURI OSAMA , MICHELONI RINO , SACCO ANDREA , TORELLI GUIDO
Abstract: A voltage generator formed of a charge circuit and a discharge circuit having a common programmable voltage divider with variable resistance; the programmable voltage divider including a plurality of resistors arranged in series and selectively connectable to define alternatively a step-wise increasing program voltage and a fixed verify voltage. The charge circuit formed of a voltage regulator supplying at the output the precise voltage value determined by the programmable voltage divider, and the discharge circuit intervening when the output voltage must be switched in a controlled manner from a higher value to a lower value.
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Patent Agency Ranking
公开(公告)号：DE69229995D1
公开(公告)日：1999-10-21
申请号：DE69229995
申请日：1992-06-30
Applicant: ST MICROELECTRONICS SRL
Inventor： FLOCCHI CARLO , TORELLI GUIDO
Abstract: A voltage regulator for electrically programmable, non-volatile memory devices, having an output terminal connected to a power supply line for programming the state of at least one memory element through at least one selection circuit means (MW,MB) and comprising at least first (R1) and second (R2) resistive elements connected between first and second terminals of a voltage supply. The regulator further comprises at least a second circuit means (MWd,MBd) being the homolog of the selection circuit means for programming the memory element, said second circuit means being connected serially to the resistive elements (R1,R2) across the two terminals of the voltage supply. Also provided is at least one controlled current generator (G1,G2) connected between one of the two voltage supply terminals and a linking node to one of the resistive elements and an operational amplifier (A) whose non-inverting (+) input is connected to a linking node to at least one of the resistive elements and whose output terminal is the output terminal of the regulator.
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公开(公告)号：DE69226627D1
公开(公告)日：1998-09-17
申请号：DE69226627
申请日：1992-05-15
Applicant: ST MICROELECTRONICS SRL
Inventor： MARCHESI GIANMARCO , TORELLI GUIDO
Abstract: A non-overlapping phase, signal generator (1) comprises first and second loop oscillators (O1,O2) including cascaded inverters. Defined in each cascade of inverters are first and second circuit nodes between the inverters. Between the first node (2) of the first oscillator and the second node (3A) of the second oscillator, there is connected a transistor having a control terminal connected to the first node of the second oscillator. Connected between the first node (2A) of the second oscillator (O2) and the second node (3) of the first oscillator is a transistor having a control terminal connected to the first node of the first oscillator (O1).
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公开(公告)号：DE69627318T2
公开(公告)日：2004-02-12
申请号：DE69627318
申请日：1996-08-22
Applicant: ST MICROELECTRONICS SRL
Inventor： ROLANDI PAOLO , CALLIGARIO CRISTIANO , MANSTRETTA ALESSANDRO , TORELLI GUIDO
Abstract: In a storage device of the multi-level type, comprising a plurality of memory cells addressable through an address input (RADR,CADR), each cell being adapted for storing more than one binary information element in a MOS transistor which has a control gate, and a floating gate for storing electrons to modify the threshold voltage of the transistor, and comprising a circuit enabling a Direct Memory Access (DMA) mode for directly accessing the memory cells from outside the device, the memory cells are programmed in the direct memory access mode by controlling, from outside the device, the amount of charge stored into the floating gate of each transistor.
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公开(公告)号：IT1321049B1
公开(公告)日：2003-12-30
申请号：ITTO20001049
申请日：2000-11-07
Applicant: ST MICROELECTRONICS SRL
Inventor： GREGORI STEFANO , FERRARI PIETRO , TORELLI GUIDO
IPC: H03M13/00
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公开(公告)号：IT1320666B1
公开(公告)日：2003-12-10
申请号：ITTO20000892
申请日：2000-09-22
Applicant: ST MICROELECTRONICS SRL
Inventor： SACCO ANDREA , KHOURI OSAMA , MICHELONI RINO , TORELLI GUIDO
Abstract: Described herein is a nonvolatile memory comprising a memory array organized according to global word lines and local word lines; a global row decoder; a local row decoder; a first supply stage for supplying the global row decoder; and a second supply stage for supplying the local row decoder; and a third supply stage for biasing the drain and source terminals of the memory cells of the memory array. Each of the supply stages comprises a respective resistive divider formed by a plurality of series-connected resistors, and a plurality of pass-gate CMOS switches each connected in parallel to a respective resistor. The nonvolatile memory further comprises a control circuit for controlling the pass-gate CMOS switches of the supply stages, and a switching circuit for selectively connecting the supply input of the control circuit to the output of the second supply stage during reading and programming of the memory, and to the output of the third supply stage during erasing of the memory.
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