公开(公告)号：EP0267361A1

公开(公告)日：1988-05-18

申请号：EP87108319.2

申请日：1987-06-09

Applicant: Microelectronics and Computer Technology Corporation

Inventor： Ghoshal, Uttam S.

IPC: H03K19/094 ,  H03K19/017

CPC classification number: H03K19/01714

Abstract: A bootstrapped CMOS driver circuit capable of driving large capacitance loads with small internal delays. Higher driving capability is achieved by using only n-channel transistors (M2, M4) at the output (O) and overdriving the transistors (M4) during the transitions. A total internal delay of less than one nanosecond for a driver may be provided with 100 ohms compatible output impedance.

Abstract translation: 一种自举的CMOS驱动电路，能够驱动大的电容负载，内部延迟小。 通过在输出（O）下仅使用n沟道晶体管（M2，M4）并在转换期间过驱动晶体管（M4）来实现更高的驱动能力。 驱动器的总内部延迟小于1纳秒可以提供100欧姆兼容的输出阻抗。

公开(公告)号：EP0745270A1

公开(公告)日：1996-12-04

申请号：EP95910308.0

申请日：1995-02-13

Applicant: MICROELECTRONICS AND COMPUTER TECHNOLOGY CORPORATION

Inventor： NOLAN, Ernest, R. ,  DUANE, Diana, Carter ,  HERDER, Todd, H. ,  BISHOP, Thomas, A. ,  TRAN, Kimcuc, T. ,  FROEHLICH, Robert, W. ,  GERMAN, Randy, L. ,  NELSON, Richard, D. ,  LEE, Chung, J. ,  BREEN, Mark, R. ,  KESWICK, Kathryn, V.

IPC: H01L23 ,  H01L21

CPC classification number: H01L24/12 ,  H01L21/563 ,  H01L23/49811 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/0231 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05599 ,  H01L2224/0603 ,  H01L2224/114 ,  H01L2224/1147 ,  H01L2224/116 ,  H01L2224/11902 ,  H01L2224/13099 ,  H01L2224/1319 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/73203 ,  H01L2224/85444 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01056 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/09701 ,  H01L2924/14 ,  H01L2924/19042 ,  Y10S438/903 ,  H01L2224/45099 ,  H01L2924/00 ,  H01L2224/85399

Abstract: Compliant electrically conductive connection bumps (10) for an adhesive flip chip (12) integrated circuit device and various methods for forming the bumps include the steps of forming polymer bumps (24) on a substrate (12) or an integrated circuit die and coating the polymer bumps with a metallization layer (26). The polymer bump forming step includes the steps of coating a polymer material on a substrate, curing the polymer, and etching the bump pattern from the polymer material. The overcoating step includes electrolessly plating a ductile metal such as gold on the polymer bump.

公开(公告)号：EP0268971B1

公开(公告)日：1993-03-24

申请号：EP87116898.5

申请日：1987-11-16

Applicant: Microelectronics and Computer Technology Corporation

Inventor： Potter, Curtis Nathan

IPC: H01L21/48 ,  H01L23/14

CPC classification number: H05K3/4685 ,  H01L21/4857 ,  H01L23/5381 ,  H01L2924/0002 ,  H05K3/205 ,  H01L2924/00

公开(公告)号：EP0267772B1

公开(公告)日：1993-01-13

申请号：EP87309904.8

申请日：1987-11-09

Applicant: Microelectronics and Computer Technology Corporation

Inventor： Herrell, Dennis, J. ,  Gupta, Omkarnath Ramnath ,  Hilbert, Claude

IPC: H01L23/467 ,  H01L23/367

CPC classification number: H01L23/467 ,  H01L23/3672 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

公开(公告)号：EP0493411A1

公开(公告)日：1992-07-08

申请号：EP90913152.0

申请日：1990-08-30

Applicant: Microelectronics and Computer Technology Corporation

Inventor： WEHRLY, James, Douglass, Jr. ,  BERTRAM, Michael, John

IPC: B21D28 ,  B26F1 ,  H01L21 ,  H01L23

CPC classification number: H01L21/67144 ,  B26F1/14 ,  B26F2210/08 ,  Y10T83/8855

Abstract: L'objet de cette invention est de fournir un alignement simple et commode entre deux outils de façonnage. Le problème technique concerne les procédures de fausse position qui prennent du temps et qu'on utilise fréquemment pour aligner des outils de façonage avec des tolérances fines, par exemple de 0,025 mils. L'invention résoud le problème de l'alignement en utilisant une pluralité d'éléments d'alignement (22) qui s'élèvent au-dessus de la surface (26) d'un outil de façonnage (14) de sorte que les éléments d'alignement (22) s'engagent par coulissement avec les glissières d'alignement (32) formées dans les coins de l'autre outil de façonnage (14). Dans certaines versions, les éléments (22) et les glissières (32) d'alignement peuvent être formés aux quatre coins des outils rectangulaires de façonnage, et les éléments d'alignement (22) peuvent être formés aux quatre coins des outils rectangulaires de façonnage, et les éléments d'alignement (22) peuvent être des tiges cylindriques avec des sommets en forme de dôme (30). L'alignement est utile pour la mise en place du façonnage ainsi que pour le façonnage lui-même. L'utilité principale de l'invention concerne l'alignement entre une perforatrice (12) et une matrice de façonnage de conduites (14) lorsqu'elles sonts rapprochées pour former des conduites externes de bande TAB (56) reliées à un circuit intégré (54).

公开(公告)号：EP0427883A1

公开(公告)日：1991-05-22

申请号：EP89121078.3

申请日：1989-11-14

Applicant: Microelectronics and Computer Technology Corporation

Inventor： Smith, Robert Travis

IPC: H01R23/68 ,  H01R13/637 ,  H01R9/07 ,  G01R1/073 ,  H05K3/36

CPC classification number: H01R12/853 ,  H05K3/365

Abstract: A zero insertion force electrical connector for electrically connecting two electrical members. A plurality of first electrical contacts on a first member engage a plurality of second electrical on a second member. An isostatic medium is retained against the second member and a pressure generator acts on the isostatic medium for providing a uniform force forcing the first and second contacts into engagement. One of the first and second contacts may be positioned in recesses and the other of the first and second contacts are outwardly extending for providing self-alignment between the first and second members. The second member may be a three-layer tape having a first metal signal layer, a middle dielectric layer and a second ground layer for interconnection to a third electrical member.

Abstract translation: 用于电连接两个电气构件的零插入力电连接器。 第一构件上的多个第一电触头在第二构件上接合多个第二电。 等静压介质被保持抵靠第二构件，并且压力发生器作用在等静压介质上，以提供强制使第一和第二触点接合的均匀的力。 第一和第二触点中的一个可以定位在凹部中，并且第一和第二触头中的另一个向外延伸以在第一和第二构件之间提供自对准。 第二构件可以是具有用于互连到第三电气构件的第一金属信号层，中间电介质层和第二接地层的三层带。

公开(公告)号：EP0310357A3

公开(公告)日：1991-01-09

申请号：EP88308996.3

申请日：1988-09-28

Applicant: Microelectronics and Computer Technology Corporation

Inventor： Carey, David H.

IPC: H05K1/00

CPC classification number: H01L23/5383 ,  H01L23/4985 ,  H01L23/5382 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48472 ,  H01L2924/09701 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0289 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A customizable circuit using a programmable interconnect and a compatible TAB chip bonding design. The programmable interconnect comprises layers of wire segments forming programmable junctions rather than continuous wires. This segmentation is performed with an offset from line to line in each layer such that the ends of the segments in each layer form along diagonal lines having a pitch determined by the basic wire segment length. The terminal ends of each of these segments are positioned in a plane such that the segments may be connected by short lengths to form the desired interconnect. The links which join the line segments represent the customization of the otherwise undedicated interconnect. The TAB chip bonding design uses a carrier tape to bond the integrated circuit chips to the programmable interconnect. Also disclosed are methods for forming the interconnect and the TAB chip bonding design.

Abstract translation: 使用可编程互连和兼容TAB芯片接合设计的可定制电路。 可编程互连包括形成可编程结而不是连续导线的线段层。 该分割是利用每一层中的线对线的偏移来执行的，使得每个层中的段的端部沿着具有由基本线段长度确定的间距的对角线形成。 这些片段中的每一个的末端位于平面中，使得片段可以通过短长度连接以形成所需的互连。 连接线段的链接代表了否定的未互连互连的定制。 TAB芯片接合设计使用载带将集成电路芯片连接到可编程互连。 还公开了用于形成互连和TAB芯片接合设计的方法。

公开(公告)号：EP0268116B1

公开(公告)日：1991-01-02

申请号：EP87115855.6

申请日：1987-10-28

Applicant: Microelectronics and Computer Technology Corporation

Inventor： Potter, Curtis Nathan

IPC: G03F7/16 ,  H01L21/312

CPC classification number: H01L21/02282 ,  G03F7/168 ,  H01L21/02118 ,  H01L21/312

Abstract: Applying a photoresist layer containing a solvent to the top of an electronic wafer by spin coating. Before the layer dries the wafer is heated in an oven while controlling the solvent loss from the coating by maintaining the pressure of the solvent vapor and providing a slow solvent loss for planarizing the top surface of the polymer. The device is removed from the first oven and the bake cycle is completed in a standard convection bake oven.

公开(公告)号：EP0351851A2

公开(公告)日：1990-01-24

申请号：EP89113348.0

申请日：1989-07-20

Applicant: Microelectronics and Computer Technology Corporation

Inventor： MacKay, Colin Alan

IPC: H01R9/07

CPC classification number: H01R12/62 ,  H01L21/486 ,  H01R12/714 ,  H05K1/0393 ,  H05K1/113 ,  H05K3/064 ,  H05K3/4007 ,  H05K3/423 ,  H05K3/427 ,  H05K2201/0347 ,  H05K2201/0355 ,  H05K2201/0367 ,  H05K2201/0394 ,  H05K2201/096 ,  H05K2201/09781 ,  H05K2201/10378 ,  H05K2203/0338 ,  H05K2203/0554 ,  H05K2203/063 ,  H05K2203/0726 ,  H05K2203/0733 ,  H05K2203/1572 ,  Y10T29/49169 ,  Y10T29/49222

Abstract: A method and apparatus for making a flexible interconnect for connection between stacks of electronic components. The method includes forming a plurality of holes through a flexible insulating material, depositing electrically conductive metal studs into the holes extending out of at least one side and preferably both sides of the flexible material, and electrically interconnecting some of the electrically conductive metal studs by interconnects supported by the flexible material. The interconnects may be supported from the outside of the flexible material or embedded therein. Dummy studs may be provided in the flexible material extending to the outside and aligned with studs extending on the other side of the insulating material which are connected to the electrical interconnects.

Abstract translation: 一种用于制造用于电子部件的堆叠之间的连接的柔性互连的方法和装置。 该方法包括通过柔性绝缘材料形成多个孔，将导电金属螺柱沉积到从弹性材料的至少一个侧面，优选两侧延伸的孔中，并且通过互连将一些导电金属螺柱电互连 由柔性材料支撑。 互连可以从柔性材料的外部支撑或嵌入其中。 虚拟螺柱可以设置在延伸到外部的柔性材料中，并且与连接到电互连的绝缘材料的另一侧上延伸的螺柱对准。

公开(公告)号：EP0328869A2

公开(公告)日：1989-08-23

申请号：EP89100490.5

申请日：1989-01-12

Applicant: Microelectronics and Computer Technology Corporation

Inventor： Woodard, Ollie Clifton, Sr. ,  Ross, Andrew William

IPC: G01R31/28 ,  G01R31/305

CPC classification number: H01J37/045 ,  G01R31/305 ,  H01J2237/24507

Abstract: An electron beam testing apparatus for applying an electron beam to parts of an electronic component and measuring the secondary electrons released from the part including a secondary electron collector having a plurality of vertically extending screens with a detector positioned adjacent one of the screens. A different voltage is applied to each of the screens of the collector for collecting the secondary electrons over a large area. The apparatus may include a combination blanking and Faraday cup for metering the electron beam current when it is blanked. The apparatus may also be used to measure net work capacitance by measuring the time required to charge a network to a predetermined voltage.

Abstract translation: 一种电子束测试装置，用于将电子束施加到电子元件的部件上，并测量从包括具有多个垂直延伸的屏幕的二次电子收集器的部件释放的二次电子，其中检测器位于一个屏幕附近。 将不同的电压施加到收集器的每个屏幕上以在大面积上收集二次电子。 该装置可以包括组合消隐和法拉第杯，用于在消隐时测量电子束电流。 该装置也可以用于通过测量将网络充电到预定电压所需的时间来测量净功功率。