Abstract:
A bootstrapped CMOS driver circuit capable of driving large capacitance loads with small internal delays. Higher driving capability is achieved by using only n-channel transistors (M2, M4) at the output (O) and overdriving the transistors (M4) during the transitions. A total internal delay of less than one nanosecond for a driver may be provided with 100 ohms compatible output impedance.
Abstract:
Compliant electrically conductive connection bumps (10) for an adhesive flip chip (12) integrated circuit device and various methods for forming the bumps include the steps of forming polymer bumps (24) on a substrate (12) or an integrated circuit die and coating the polymer bumps with a metallization layer (26). The polymer bump forming step includes the steps of coating a polymer material on a substrate, curing the polymer, and etching the bump pattern from the polymer material. The overcoating step includes electrolessly plating a ductile metal such as gold on the polymer bump.
Abstract:
L'objet de cette invention est de fournir un alignement simple et commode entre deux outils de façonnage. Le problème technique concerne les procédures de fausse position qui prennent du temps et qu'on utilise fréquemment pour aligner des outils de façonage avec des tolérances fines, par exemple de 0,025 mils. L'invention résoud le problème de l'alignement en utilisant une pluralité d'éléments d'alignement (22) qui s'élèvent au-dessus de la surface (26) d'un outil de façonnage (14) de sorte que les éléments d'alignement (22) s'engagent par coulissement avec les glissières d'alignement (32) formées dans les coins de l'autre outil de façonnage (14). Dans certaines versions, les éléments (22) et les glissières (32) d'alignement peuvent être formés aux quatre coins des outils rectangulaires de façonnage, et les éléments d'alignement (22) peuvent être formés aux quatre coins des outils rectangulaires de façonnage, et les éléments d'alignement (22) peuvent être des tiges cylindriques avec des sommets en forme de dôme (30). L'alignement est utile pour la mise en place du façonnage ainsi que pour le façonnage lui-même. L'utilité principale de l'invention concerne l'alignement entre une perforatrice (12) et une matrice de façonnage de conduites (14) lorsqu'elles sonts rapprochées pour former des conduites externes de bande TAB (56) reliées à un circuit intégré (54).
Abstract:
A zero insertion force electrical connector for electrically connecting two electrical members. A plurality of first electrical contacts on a first member engage a plurality of second electrical on a second member. An isostatic medium is retained against the second member and a pressure generator acts on the isostatic medium for providing a uniform force forcing the first and second contacts into engagement. One of the first and second contacts may be positioned in recesses and the other of the first and second contacts are outwardly extending for providing self-alignment between the first and second members. The second member may be a three-layer tape having a first metal signal layer, a middle dielectric layer and a second ground layer for interconnection to a third electrical member.
Abstract:
A customizable circuit using a programmable interconnect and a compatible TAB chip bonding design. The programmable interconnect comprises layers of wire segments forming programmable junctions rather than continuous wires. This segmentation is performed with an offset from line to line in each layer such that the ends of the segments in each layer form along diagonal lines having a pitch determined by the basic wire segment length. The terminal ends of each of these segments are positioned in a plane such that the segments may be connected by short lengths to form the desired interconnect. The links which join the line segments represent the customization of the otherwise undedicated interconnect. The TAB chip bonding design uses a carrier tape to bond the integrated circuit chips to the programmable interconnect. Also disclosed are methods for forming the interconnect and the TAB chip bonding design.
Abstract:
Applying a photoresist layer containing a solvent to the top of an electronic wafer by spin coating. Before the layer dries the wafer is heated in an oven while controlling the solvent loss from the coating by maintaining the pressure of the solvent vapor and providing a slow solvent loss for planarizing the top surface of the polymer. The device is removed from the first oven and the bake cycle is completed in a standard convection bake oven.
Abstract:
A method and apparatus for making a flexible interconnect for connection between stacks of electronic components. The method includes forming a plurality of holes through a flexible insulating material, depositing electrically conductive metal studs into the holes extending out of at least one side and preferably both sides of the flexible material, and electrically interconnecting some of the electrically conductive metal studs by interconnects supported by the flexible material. The interconnects may be supported from the outside of the flexible material or embedded therein. Dummy studs may be provided in the flexible material extending to the outside and aligned with studs extending on the other side of the insulating material which are connected to the electrical interconnects.
Abstract:
An electron beam testing apparatus for applying an electron beam to parts of an electronic component and measuring the secondary electrons released from the part including a secondary electron collector having a plurality of vertically extending screens with a detector positioned adjacent one of the screens. A different voltage is applied to each of the screens of the collector for collecting the secondary electrons over a large area. The apparatus may include a combination blanking and Faraday cup for metering the electron beam current when it is blanked. The apparatus may also be used to measure net work capacitance by measuring the time required to charge a network to a predetermined voltage.