公开(公告)号：KR1020130010439A

公开(公告)日：2013-01-28

申请号：KR1020120077970

申请日：2012-07-17

Applicant: 한국전자통신연구원

Inventor： 황동거 ,  김천수 ,  박필재 ,  박민 ,  유현규

IPC: H04B1/16 ,  H04B1/04 ,  H04L25/03

CPC classification number: H04B1/38 ,  H03G1/0088 ,  H03G3/001

Abstract: PURPOSE: A baseband structure of a transceiver is provided to selectively operate a fixed gain amplifier according to necessary gain and to reduce the size of a chip and power consumption. CONSTITUTION: A variable gain amplifier(VGA) controls gain. The variable gain amplifier amplifies an input signal. At least one fixed gain amplifier(FGA) is serially connected to the variable gain amplifier. The fixed gain amplifier amplifies an output signal of the variable gain amplifier. At least one or more selection switches selectively operate the fixed gain amplifiers.

Abstract translation: 目的：提供收发器的基带结构，以根据必要的增益选择性地操作固定增益放大器，并减小芯片的尺寸和功耗。 构成：可变增益放大器（VGA）控制增益。 可变增益放大器放大输入信号。 至少一个固定增益放大器（FGA）串联连接到可变增益放大器。 固定增益放大器放大可变增益放大器的输出信号。 至少一个或多个选择开关选择性地操作固定增益放大器。

公开(公告)号：KR1020120106567A

公开(公告)日：2012-09-26

申请号：KR1020120023430

申请日：2012-03-07

Applicant: 한국전자통신연구원

Inventor： 김천수 ,  박필재 ,  박민 ,  박경환 ,  김동영 ,  김정근 ,  구본태 ,  유현규

IPC: G01S13/88 ,  B60W40/02 ,  B60W30/08

CPC classification number: G01S13/88 ,  B60W30/08 ,  B60W40/02

Abstract: PURPOSE: A radar device for simultaneously supporting a short range radar function and a long range radar function is provided to implement high integration by forming components on a single chip. CONSTITUTION: An antenna unit(210) includes a transmission array antenna(211) and a reception array antenna(212). A transmitting unit(220) generates a plurality of chirp signals for long range transmission and a plurality of chirp signals for short range transmission by an FMCW(frequency modulated continuous-wave) modulation method and transmits the chirp signals using the transmission array antenna. A receiving unit processes a reflective wave signal received by the reception array antenna. A signal processor(231) generates a control signal for generating the plurality of the chirp signals for long range transmission and the plurality of the chirp signals for short range transmission and processes the signal from the receiving unit.

Abstract translation: 目的：提供同时支持短距离雷达功能和远程雷达功能的雷达设备，通过在单个芯片上形成组件来实现高集成度。 构成：天线单元（210）包括发射阵列天线（211）和接收阵列天线（212）。 发送单元（220）通过FMCW（调频连续波）调制方式生成用于长距离发送的多个线性调频信号和用于短距离发送的多个线性调频信号，并使用发送阵列天线发送线性调频信号。 接收单元处理由接收阵列天线接收的反射波信号。 信号处理器（231）产生用于产生用于远距离传输的多个线性调频脉冲信号的控制信号和用于短距离传输的多个线性调频信号，并处理来自接收单元的信号。

公开(公告)号：KR100880448B1

公开(公告)日：2009-01-29

申请号：KR1020070080480

申请日：2007-08-10

Applicant: 한국전자통신연구원

Inventor： 박민 ,  강태영 ,  최병건 ,  최윤호 ,  김병조 ,  김영호 ,  박경환 ,  현석봉 ,  엄낙웅

IPC: H03F3/20

CPC classification number: H03G3/3042 ,  H03F1/0261 ,  H03F1/0277 ,  H03F1/32 ,  H03F3/211 ,  H03F3/72 ,  H03F2200/318 ,  H03F2200/451 ,  H03F2203/21103 ,  H03F2203/21139 ,  H03F2203/7233

Abstract: The low dissipation mixed mode power amplifier is provided to extend the life time of battery by maximizing the efficiency of the maximum usage frequency region. The mixed mode power amplifier(1000) comprises the low output amplifier circuit(1100), the high power amplification circuit(1200), and the amplifier control part(950) and bias circuit(900). The low output amplifier circuit comprises the input impedance conformable part(100), the primary amplification section(200), and the first mid-stage impendence matching line(300) and low output amplifier(700). The high power amplification circuit(1200) comprises the second amplifier(400), and the second mid-stage impendence matching line(500) and high power amplifier(600).

Abstract translation: 提供了低耗散混合模式功率放大器，通过最大化最大使用频率区域的效率来延长电池的使用寿命。 混合模式功率放大器（1000）包括低输出放大器电路（1100），高功率放大电路（1200）和放大器控制部分（950）和偏置电路（900）。 低输出放大器电路包括输入阻抗一致部分（100），初级放大部分（200）和第一中级阻抗匹配线（300）和低输出放大器（700）。 高功率放大电路（1200）包括第二放大器（400）和第二中间阻抗匹配线（500）和高功率放大器（600）。

公开(公告)号：KR100396919B1

公开(公告)日：2003-09-02

申请号：KR1020000082809

申请日：2000-12-27

Applicant: 한국전자통신연구원

Inventor： 박민 ,  문재경 ,  임종원 ,  남은수 ,  김해천

IPC: H01L29/737

Abstract: PURPOSE: A method for fabricating a semiconductor integrated device is provided to integrate a digital integrated circuit(IC), an analog IC and a radio frequency(RF) IC, by embodying an AlGaAs/GaAs heterojunction bipolar transistor(HBT) semiconductor integrated device for ultrahigh frequency telecommunication. CONSTITUTION: A base region is formed in a predetermined region of a semiconductor substrate(31). The first insulation layer is formed in a defined base region and on the entire substrate. An emitter region is formed in the first insulation layer in the base region. An emitter electrode is formed in the emitter region. A base electrode is formed on the base region. A collector region is formed in the first insulation layer to fabricate a collector electrode. A predetermined region of the emitter electrode and collector electrode is exposed to form the first metal interconnection. The second insulation layer planarized by the first metal interconnection process is formed. A contact hole is formed in the second insulation layer and a metal interconnection is deposited. The metal interconnection is lifted off to form the second metal interconnection connected to the first metal interconnection.

Abstract translation: 本发明提供了一种用于制造半导体集成器件的方法，该器件通过包含AlGaAs / GaAs异质结双极晶体管（HBT）半导体集成器件来集成数字集成电路（IC），模拟IC和射频（RF）IC 超高频电信。 构成：在半导体衬底（31）的预定区域中形成基极区域。 第一绝缘层形成在限定的基底区域中并且形成在整个基底上。 发射极区域形成在基极区域中的第一绝缘层中。 发射极电极形成在发射极区域中。 基极形成在基极区域上。 集电极区域形成在第一绝缘层中以制造集电极。 发射极电极和集电极电极的预定区域被暴露以形成第一金属互连。 形成通过第一金属互连工艺平坦化的第二绝缘层。 在第二绝缘层中形成接触孔并沉积金属互连。 金属互连被提起以形成连接到第一金属互连的第二金属互连。

公开(公告)号：KR1020030056332A

公开(公告)日：2003-07-04

申请号：KR1020010086533

申请日：2001-12-28

Applicant: 한국전자통신연구원

Inventor： 김해천 ,  박민 ,  문재경 ,  형창희 ,  지홍구 ,  안호균

IPC: H01L27/04

CPC classification number: H01L29/7785

Abstract: PURPOSE: A PHEMT(Pseudomorphic High Electron Mobility Transistor) power device and a method for manufacturing the same are provided to be capable of using a single power supply, improving linearity, and increasing breakdown voltage. CONSTITUTION: A GaAs buffer layer(12), an AlGaAs/GaAs superlattice layer(14), an undoped AlGaAs layer(16) having a wide band gap, the first silicon doped layer(20), the first spacer(22), an InGaAs electron moving layer(24), the second spacer(26), the second silicon doped layer(28), a lightly doped AlGaAs layer(30), and an undoped GaAs capping layer(32) are sequentially formed on a GaAs semi-insulating substrate(10). A source and drain electrode(42,44) are located on the undoped GaAs capping layer for the ohmic contact between the undoped GaAs capping layer and the source and drain electrode. A gate electrode(60) is located on the lightly doped AlGaAs layer through the undoped GaAs capping layer.

Abstract translation: 目的：提供PHEMT（伪态高电子迁移率晶体管）功率器件及其制造方法，以能够使用单个电源，提高线性度和增加击穿电压。 构成：GaAs缓冲层（12），AlGaAs / GaAs超晶格层（14），具有宽带隙的未掺杂的AlGaAs层（16），第一硅掺杂层（20），第一间隔物（22）， 在GaAs半导体层上依次形成InGaAs电子移动层（24），第二间隔物（26），第二硅掺杂层（28），轻掺杂AlGaAs层（30）和未掺杂的GaAs覆盖层（32） 绝缘基板（10）。 源极和漏极（42,44）位于未掺杂的GaAs覆盖层上，用于未掺杂的GaAs覆盖层与源极和漏极之间的欧姆接触。 栅电极（60）通过未掺杂的GaAs覆盖层位于轻掺杂的AlGaAs层上。

公开(公告)号：KR100345397B1

公开(公告)日：2002-07-26

申请号：KR1019990062446

申请日：1999-12-27

Applicant: 한국전자통신연구원

Inventor： 한선호 ,  유현규 ,  김충환 ,  김천수 ,  박민

IPC: H03L7/00

Abstract: 본발명은기준신호와비교신호를비교하여위상차신호를생성하는위상비교기와, 위상비교기로부터의위상차신호에기초한펄스성분을포함하는 DC 성분을갖는전압신호를생성하는차지펌프와, 차지펌프로부터공급된전압신호를평활화하여고주파성분이제거된제어전압을생성하는로우패스필터와, 주파수가제어전압의값에대응하는출력신호를출력하는전압제어발진기와, 전압제어발진기로부터생성된출력신호는피드백하는분주회로를구비하는주파수합성기에있어서, 분주회로는복수의상단 T 플립플롭과, 복수의하단 D 플립플롭을구비함으로써, 분주회로에의한지연시간을단축시키는주파수합성기를제공한다.

公开(公告)号：KR100296146B1

公开(公告)日：2001-08-07

申请号：KR1019980018711

申请日：1998-05-23

Applicant: 한국전자통신연구원

Inventor： 김충환 ,  김천수 ,  유현규 ,  현영철 ,  박민

IPC: H04B1/62

Abstract: PURPOSE: A small signal linearizing apparatus is provided to improve linearity by feedbacking a nonlinear signal generated from a nonlinear signal generator to an amplifying unit through a feedback unit, amplifying the nonlinear signal to have the opposite phase of the nonlinear component of a small signal amplified through the amplifying unit and canceling the nonlinear component of the amplified small signal. CONSTITUTION: The first and second DC signal cut-off unit(610) are connected to an input terminal(IN). An amplifying unit(630) is connected to the first DC signal cut-off unit(610). The first input signal leakage preventing unit includes one terminal to which a DC bias is applied and the other terminal connected to the input terminal of the amplifying unit(630). A nonlinear signal generating unit is connected in parallel to the amplifying unit(630) and has an input terminal connected to the second DC signal cut-off unit. The second input signal leakage preventing unit(660) includes one terminal to which the DC bias(VGG2) is applied and the other terminal connected to the input terminal of the nonlinear signal generating unit. A load(670) is connected between a power(VDD) and an output terminal(OUT). A feedback unit(680) is connected between the input terminal of the amplifying unit(630) and the output terminal of the nonlinear signal generating unit. A load(690) is connected between the power(VDD) and the output terminal of the nonlinear signal generating unit.

公开(公告)号：KR1020010027910A

公开(公告)日：2001-04-06

申请号：KR1019990039890

申请日：1999-09-16

Applicant: 한국전자통신연구원

Inventor： 김충환 ,  김천수 ,  유현규 ,  박민 ,  김대용

IPC: H03D7/00

Abstract: PURPOSE: A mixer of Gibert cell frequency by using a unipolar switch is provided to reduce loss of gain of converting by supplying the condition of bias optimized by the operation of a unipolar switch. CONSTITUTION: A mixer of Gibert cell frequency by using a unipolar switch includes six FETs(Field Effect Transistors). The radio frequency signal is permitted to the gate of a FET(F311) and the electric current lD1 flows in the drain. The reverse radio frequency signal is permitted to the gate of a FET(F312) and the electric current lD2 flows in the drain. The partial oscillator signal is permitted to the gate of the FET(F313) and the drain of the FET(F313) is connected to the source of the FETs(F311, F312) in common. The radio frequency signal(RF) is permitted to the gate of the FET(F314) and the electric current lD3 flows in the drain connected with the drain of the FET(F311). The reverse radio frequency signal(/RF) is permitted to the gate of the FET(F315) and the electric current lD4 flows in the drain connected with the drain of the FET(F312). The the reverse partial oscillator signal(/LO) is permitted to the gate of the FET(F316) and the drain is connected to the source of the FETs(F314, F315) in common.

Abstract translation: 目的：提供通过使用单极开关的Gibert电池频率的混频器，通过提供通过单极开关的操作优化的偏置条件来减少转换增益的损失。 构成：使用单极开关的Gibert电池频率的混频器包括六个FET（场效应晶体管）。 射频信号被允许到FET的栅极（F311），电流ID1流入漏极。 反向射频信号被允许到FET的栅极（F312），并且电流ID2流入漏极。 部分振荡器信号被允许到FET的栅极（F313），并且FET（F313）的漏极共同连接到FET的源极（F311，F312）。 允许射频信号（RF）到FET（F314）的栅极，并且电流ID3流过与FET（F311）的漏极连接的漏极。 反向射频信号（/ RF）被允许到FET的栅极（F315），并且电流ID4流过与FET的漏极连接的漏极（F312）。 反向部分振荡器信号（/ LO）被允许到FET（F316）的栅极，漏极与FET（F314，F315）的源极共同连接。

公开(公告)号：KR100275541B1

公开(公告)日：2001-01-15

申请号：KR1019970070321

申请日：1997-12-19

Applicant: 한국전자통신연구원

Inventor： 유현규 ,  박민 ,  이상국 ,  남기수

IPC: H01L27/06

Abstract: PURPOSE: A structure of a high frequency resonance circuit for arranging a capacitor in an internal diameter of an inductor and a method for designing the same are provided to reduce an area of a resonance circuit by forming an integrated inductor in an internal diameter of an inductor. CONSTITUTION: An inductor is formed with a metallic line(20) of N layer as an input terminal, metallic lines(22,26) of N-1 layer connected through a contact hole(21) of the input terminal of the metallic layer(20) and a contact hole(25) of a termination of the metallic layer(20), and an inter-metal insulating layer between a lower portion of the metallic line(20) of N layer and an upper portion of the metallic lines(22,26) of N-1 layer. A high frequency resonance circuit is formed with a polysilicon layer(28) of M layer connected with the metallic layer(26) and the contact hole(25), a polysilicon layer(24) of M-1 layer, and an inter-polysilicon insulating layer.

Abstract translation: 目的：提供一种用于布置电感器内径中的电容器的高频谐振电路的结构及其设计方法，以通过在电感器的内径中形成集成电感器来减小谐振电路的面积 。 构成：电感器由N层的金属线（20）形成为输入端子，N-1层的金属线（22,26）通过金属层的输入端子的接触孔（21）连接（ 20）和金属层（20）的端接件的接触孔（25），以及在N层金属线（20）的下部与金属线的上部之间的金属间绝缘层（ 22,26）N-1层。 高频谐振电路形成有与金属层（26）和接触孔（25）连接的M层的多晶硅层（28），M-1层的多晶硅层（24）和多晶硅 绝缘层。

公开(公告)号：KR100194599B1

公开(公告)日：1999-07-01

申请号：KR1019950042597

申请日：1995-11-21

Applicant: 한국전자통신연구원

Inventor： 박종문 ,  구진근 ,  김기홍 ,  현영철 ,  박민

IPC: H01J31/15

CPC classification number: H01J9/025

Abstract: 본 발명은 실리콘 팁을 갖는 필드 에미션 디스플레이 소자 제조방법에 관한 것으로서,종래기술의 열산화막을 마스킹층으로 활용하여 실리콘 식각을 수행함으로써 제조공정이 복잡하고 팁의 전자방출 효율이 저하되며,흠의 발생빈도가 높았던 문제점을 해결하기 위해 본 발명은 감광막 패턴을 마스킹층으로 하여 언더 컷(under-cut)형태의 단면형상 특성을 갖는 실리콘 팁을 실리콘 기판을 식각해서 얻은 후 실리콘 팁 위에와 실리콘 팁을 실리콘 기판을 식각해서 얻은 후 실리콘 팁 위에와 실리콘 팁 이외의 부분에서 단차 피복성이 좋지 않은 증착 산화막을 동시에 형성시킬 때 서로 분리되어 형성됨으로써 제조공정 감축, 흠 발생빈도 감소에 따른 수율 향상,팁의 방출효성을 향상등의 효과를 얻을 수 있는 것이다.