Verfahren zum Herstellen eines Halbleiterbauelements und Halbleiterbauelement

    公开(公告)号:DE102009059236A1

    公开(公告)日:2010-07-01

    申请号:DE102009059236

    申请日:2009-12-21

    Abstract: Die Erfindung betrifft ein Verfahren zum Herstellen eines Bauelements (100), wobei mehrere Module (10) bereitgestellt werden, jedes der Module (10) einen Träger (11) und mindestens einen an dem Träger (11) angebrachten Halbleiterchip (12) umfasst, eine dielektrische Schicht (13) auf den Modulen (10) aufgebracht wird, um ein Werkstück (14) auszubilden, die dielektrische Schicht (13) strukturiert wird, um mindestens einen der Halbleiterchips (12) zu öffnen, und das Werkstück (14) vereinzelt wird, um mehrere Bauelemente (100) zu erhalten.

    43.
    发明专利
    未知

    公开(公告)号:DE102009040556A1

    公开(公告)日:2010-04-08

    申请号:DE102009040556

    申请日:2009-09-08

    Abstract: A coating composition including a compound having a first molecular group or a first combination of atoms, the first molecular group or the first combination of atoms capable of bonding to an oxidizable metal or a metal oxide, and a second molecular group or a second combination of atoms, the second molecular group or the second combination of atoms capable of interacting with a precursor of a polymer so the compound and the polymer are bound together.

    44.
    发明专利
    未知

    公开(公告)号:DE102009021083A1

    公开(公告)日:2009-12-17

    申请号:DE102009021083

    申请日:2009-05-13

    Abstract: A chip carrier includes first, second and third layers with the second layer situated between the first and third layers. The first and third layers are formed of a first material and the second layer is formed of a second material. The second layer has a plurality of holes extending therethrough and the first material fills the holes.

    46.
    发明专利
    未知

    公开(公告)号:DE102009005650A1

    公开(公告)日:2009-08-13

    申请号:DE102009005650

    申请日:2009-01-22

    Abstract: A multi-chip module and method is disclosed. One embodiment provides an electronic module having a first metal structure and a second metal structure. A first semiconductor chip is electrically connected with its back side to the first metal structure. A second semiconductor chip is arranged with its back side lying over the front side of the first semiconductor chip. The second metal structure includes multiple external contact elements attached over the front side of the second semiconductor chip. At least two of the multiple external contact elements are electrically connected to the front side of the second semiconductor chip.

    47.
    发明专利
    未知

    公开(公告)号:DE102008039389A1

    公开(公告)日:2009-04-16

    申请号:DE102008039389

    申请日:2008-08-22

    Abstract: A semiconductor device and method is disclosed. One embodiment provides a substrate and a first semiconductor chip applied over the substrate. A first electrically conductive layer is applied over the substrate and the first semiconductor chip. A first electrically insulating layer is applied over the first electrically conductive layer. A second electrically conductive layer is applied over the first electrically insulating layer.

    48.
    发明专利
    未知

    公开(公告)号:DE102008045744A1

    公开(公告)日:2009-04-02

    申请号:DE102008045744

    申请日:2008-09-04

    Abstract: A semiconductor package includes a substrate, at least one chip including a first side and a backside opposite of the first side, the first side electrically coupled to the substrate, a conductive layer coupled to the backside of the at least one chip, and at least one electronic component coupled to the conductive layer and in electrical communication with the substrate.

    50.
    发明专利
    未知

    公开(公告)号:DE502005005325D1

    公开(公告)日:2008-10-23

    申请号:DE502005005325

    申请日:2005-02-09

    Abstract: A semiconductor component including a stack of semiconductor chips, the semiconductor chips being fixed cohesively one on top of another, is disclosed. The contact areas of the semiconductor chips are led as far as the edges of the semiconductor chips and conductor portions extend at least from an upper edge to a lower edge of the edge sides of the semiconductor chips in order to electrically connect the contact area of the stacked semiconductor chips to one another.

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