公开(公告)号：MY149595A

公开(公告)日：2013-09-13

申请号：MYPI20084358

申请日：2007-05-04

Applicant: LAM RES CORP

Inventor： YOON HYUNGSUK ALEXANDER ,  BAILEY ANDREW D III ,  RYDER JASON A ,  WILCOXSON MARK H ,  GASPARITSCH JEFFREY G ,  JOHNSON RANDY ,  HOFFMANN STEPHAN P

IPC: B08B7/00

Abstract: AN APPARATUS, SYSTEM AND METHOD FOR CLEANING A SUBSTRATE EDGE (101) INCLUDE A BRISTLE BRUSH UNIT (200) THAT CLEANS BEVEL POLYMERS (103) DEPOSITED ON SUBSTRATE EDGES USING FRICTIONAL CONTACT IN THE PRESENCE OF CLEANING CHEMISTRY. THE BRISTLE BRUSH UNIT IS MADE UP OF A PLURALITY OF OUTWARDLY EXTENDING VANES (201) AND IS MOUNTED ON A ROTATING SHAFT (202). AN ABRASIVE MATERIAL IS DISTRIBUTED THROUGHOUT AND WITHIN THE OUTWARDLY EXTENDING VANES OF THE BRISTLE BRUSH UNIT TO PROVIDE THE FRICTIONAL CONTACT. THE BRISTLE BRUSH UNIT CLEANS THE EDGE OF THE SUBSTRATE BY ALLOWING FRICTIONAL CONTACT OF THE PLURALITY OF ABRASIVE PARTICLES WITH THE EDGE OF THE SUBSTRATE IN THE PRESENCE OF FLUIDS, SUCH AS CLEANING CHEMISTRY, TO CUT, RIP AND TEAR THE BEVEL POLYMER FROM THE EDGE OF THE SUBSTRATE.

公开(公告)号：SG174500A1

公开(公告)日：2011-10-28

申请号：SG2011068251

申请日：2010-04-05

Applicant: LAM RES CORP

Inventor： JI BING ,  TAKESHITA KENJI ,  BAILEY ANDREW D III ,  HUDSON ERIC A ,  MORAVEJ MARYAM ,  SIRARD STEPHEN M ,  KO JUNGMIN ,  LE DANIEL ,  HEFTY ROBERT C ,  CHENG YU ,  DELGADINO GERATDO A ,  YEN BI-MING

Abstract: A method for etching features in a low-k dielectric layer disposed below an organic mask is provided by an embodiment of the invention. Features are etched into the low-k dielectric layer through the organic mask. A fluorocarbon layer is deposited on the low-k dielectric layer. The fluorocarbon layer is cured. The organic mask is stripped.

公开(公告)号：SG131933A1

公开(公告)日：2007-05-28

申请号：SG2007024607

申请日：2004-12-06

Applicant: LAM RES CORP

Inventor： BAILEY ANDREW D III ,  NI TUQIANG

IPC: H01J37/32 ,  H01L21/00 ,  H01L21/302 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/44 ,  H01L21/461 ,  H01L21/4763 ,  H01L21/683 ,  H01L21/768 ,  H01L23/48 ,  H01L23/52 ,  H01L29/24 ,  H01L29/40 ,  H01L33/00

Abstract: A system and method of processing a substrate including loading a substrate into a plasma chamber and setting a pressure of the plasma chamber to a pre- determined pressure set point. Several inner surfaces that define a plasma zone are heated to a processing temperature of greater than about 200 degrees C. A process gas is injected into the plasma zone to form a plasma and the substrate us processed.

公开(公告)号：AU2003228799A1

公开(公告)日：2003-11-11

申请号：AU2003228799

申请日：2003-05-01

Applicant: LAM RES CORP

Inventor： HOWALD ARTHUR M ,  KUTHI ANDRAS ,  BAILEY ANDREW D III ,  BERNEY BUTCH

IPC: H05H1/46 ,  C23C16/00 ,  C23C16/50 ,  H01J37/32 ,  H01L21/205 ,  H01L21/306 ,  H01L21/3065 ,  H05H1/00

Abstract: A plasma processing chamber for processing a substrate to form electronic components thereon is disclosed. The plasma processing chamber includes a plasma-facing component having a plasma-facing surface oriented toward a plasma in the plasma processing chamber during processing of the substrate, the plasma-facing component being electrically isolated from a ground terminal. The plasma processing chamber further includes a grounding arrangement coupled to the plasma-facing component, the grounding arrangement including a first resistance circuit disposed in a first current path between the plasma-facing component and the ground terminal. The grounding arrangement further includes a RF filter arrangement disposed in at least one other current path between the plasma-facing component and the ground terminal, wherein a resistance value of the first resistance circuit is selected to substantially eliminate arcing between the plasma and the plasma-facing component during the processing of the substrate.

公开(公告)号：AU1490301A

公开(公告)日：2001-05-30

申请号：AU1490301

申请日：2000-11-14

Applicant: LAM RES CORP

Inventor： BAILEY ANDREW D III ,  SCHOEPP ALAN M ,  SMITH MICHAEL G R ,  KUTHI ANDRAS

IPC: H05H1/46 ,  H01J37/32 ,  H01L21/3065

Abstract: A plasma processing system that includes a temperature management system and method that can achieve very accurate temperature control over a plasma processing apparatus is disclosed. In one embodiment, the temperature management system and method operate to achieve tight temperature control over surfaces of the plasma processing apparatus which interact with the plasma during fabrication of semiconductor devices. The tight temperature control offered by the invention can be implemented with combination heating and cooling blocks such that both heating and cooling can be provided from the same thermal interface.

公开(公告)号：SG10201505975QA

公开(公告)日：2015-09-29

申请号：SG10201505975Q

申请日：2011-06-22

Applicant: LAM RES CORP

Inventor： DHINDSA RAJINDER ,  MARAKHATNOV ALEXEI ,  BAILEY ANDREW D III

公开(公告)号：SG187610A1

公开(公告)日：2013-03-28

申请号：SG2013006317

申请日：2011-06-22

Applicant: LAM RES CORP

Inventor： DHINDSA RAJINDER ,  MARAKHATNOV ALEXEI ,  BAILEY ANDREW D III

Abstract: A semiconductor wafer processing apparatus includes a first electrode exposed to a first plasma generation volume, a second electrode exposed to a second plasma generation volume, and a gas distribution unit disposed between the first and second plasma generation volumes. The first electrode is defined to transmit radio frequency (RF) power to the first plasma generation volume, and distribute a first plasma process gas to the first plasma generation volume. The second electrode is defined to transmit RF power to the second plasma generation volume, and hold a substrate in exposure to the second plasma generation volume. The gas distribution unit includes an arrangement of through-holes defined to fluidly connect the first plasma generation volume to the second plasma generation volume. The gas distribution unit also includes an arrangement of gas supply ports defined to distribute a second plasma process gas to the second plasma generation volume.

公开(公告)号：SG185251A1

公开(公告)日：2012-11-29

申请号：SG2012070876

申请日：2008-09-29

Applicant: LAM RES CORP

Inventor： BAILEY ANDREW D III

Abstract: WAFER BOW METROLOGY ARRANGEMENTS AND METHODS THEREOF AbstractAn arrangement for quantifying a wafer bow. The arrangement is positioned within a plasma processing system is provided. The arrangement includes a support mechanism for holding a wafer. The arrangement also includes a first set of sensors, which is configured to collect a first set of measurement data for a plurality of data points on the wafer. The first set of measurement data indicates a minimum gap between the first set of sensors and the wafer. The first set of sensors is positioned in a first location, which is outside of a set of process modules of the plasma processing system. Fig. 2

公开(公告)号：AU2003299054A1

公开(公告)日：2004-04-19

申请号：AU2003299054

申请日：2003-09-26

Applicant: LAM RES CORP

Inventor： YADAV PUNEET ,  BAILEY ANDREW D III

IPC: H01L21/66

公开(公告)号：AU2003277020A1

公开(公告)日：2004-04-19

申请号：AU2003277020

申请日：2003-09-24

Applicant: LAM RES CORP

Inventor： YADAV PUNEET ,  MISRA PRATIK ,  BAILEY ANDREW D III

IPC: H01L21/66

Abstract: A system and method of for determining multiple uniformity metrics of a semiconductor wafer manufacturing process includes collecting a quantity across each one of a group of semiconductor wafers. The collected quantity data is scaled and a principal component analysis (PCA) is performed on the collected, scaled quantity data to produce a first set of metrics for the first group of semiconductor wafers. The first set of metrics including a first loads matrix and a first scores matrix.