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    41.
    发明专利
    未知

    公开(公告)号：FR2783093A1

    公开(公告)日：2000-03-10

    申请号：FR9811221

    申请日：1998-09-04

    Applicant: ST MICROELECTRONICS SA

    Inventor： DELPECH PHILIPPE ,  ROBILLIART ETIENNE ,  DUTARTRE DIDIER

    IPC: H01L21/02 ,  H01L29/92

    Abstract: Built-in capacitance (C1) on a silicon substrate (7) comprises a first highly doped polysilicon electrode (1), a thin layer (3) of silicon oxide, a second polysilicon electrode (10) and a silicide layer (4) over the second electrode. The second electrode has a high dopant concentration at the interface with the silicon oxide and a relatively low dopant concentration at the interface with the silicide layer. An Independent claim is also included for an integrated circuit, comprising at least one capacitance as above.

    PROCEDE DE FORMATION D'UN TRANSISTOR MOS A CANAL EN SILICIUM-GERMANIUM
    45.
    发明专利
    PROCEDE DE FORMATION D'UN TRANSISTOR MOS A CANAL EN SILICIUM-GERMANIUM 未知

    公开(公告)号：FR2952225A1

    公开(公告)日：2011-05-06

    申请号：FR0957769

    申请日：2009-11-03

    Applicant: ST MICROELECTRONICS SA ,  ST MICROELECTRONICS CROLLES 2

    Inventor： DUTARTRE DIDIER ,  CAMPIDELLI YVES ,  LOUBET NICOLAS

    IPC: H01L21/335 ,  H01L21/8238 ,  H01L29/78

    Abstract: L'invention concerne un procédé de formation de transistors MOS, comprenant les étapes suivantes : former des tranchées isolantes (42) dans un substrat de silicium (40), lesdites tranchées délimitant des premières et des secondes zones actives (TN, Tp) ; graver une portion supérieure des premières zones actives (Tp) ; épitaxier une couche de silicium-germanium (48) dans les portions gravées ; et former des grilles de transistors PMOS (52) sur les premières zones actives et des grilles de transistors NMOS (50) sur les secondes zones actives (TN), les grilles de transistors PMOS et les grilles de transistors NMOS étant constituées d'empilements métalliques (22, 24) d'épaisseurs différentes qui s'étendent sur une région isolante à forte constante diélectrique (18, 20), la profondeur de gravure et l'épaisseur de la couche de silicium-germanium étant telles que les niveaux des surfaces des grilles des transistors NMOS et des grilles des transistors PMOS sont ajustés de façon prédéterminée.

    46.
    发明专利
    未知

    公开(公告)号：DE602007004139D1

    公开(公告)日：2010-02-25

    申请号：DE602007004139

    申请日：2007-03-16

    Applicant: ST MICROELECTRONICS CROLLES 2 ,  ST MICROELECTRONICS SA

    Inventor： MONFRAY STEPHANE ,  SKOTNICKI THOMAS ,  DUTARTRE DIDIER ,  TALBOT ALEXANDRE

    IPC: H01L29/786

    Abstract: The method involves forming an intermediate semiconductor layer (6) above a substrate (2), where the layer contains an alloy of silicon and germanium. Source, drain and insulated gate regions (11,12,9) of a MOS transistor are formed above the semiconductor layer. The semiconductor layer is oxidized from a lower surface of the layer for increasing concentration of germanium in a channel of the transistor.

    47.
    发明专利
    未知

    公开(公告)号：FR2915023B1

    公开(公告)日：2009-07-17

    申请号：FR0702696

    申请日：2007-04-13

    Applicant: ST MICROELECTRONICS CROLLES 2 ,  ST MICROELECTRONICS SA

    Inventor： DUTARTRE DIDIER ,  CORONEL PHILIPPE ,  LOUBET NICOLAS

    IPC: H01L21/48 ,  H01L21/20

    Abstract: Metal contacts are self-positioned on a wafer of semiconductor product. Respective placement areas for a metal contact are determined by a selective deposition of a growth material over a region of the substrate surface (for example, through epitaxial growth). The growth material is surrounded by an insulating material. The grown material is then removed to form a void in the insulating material which coincides with the desired location of the metal contact. This removal of the grown material exposes the region on the substrate surface. Conductive material is then deposited to fill the void and thus form the metal contact directly with the region of the substrate surface.

    50.
    发明专利
    未知

    公开(公告)号：DE69821560T2

    公开(公告)日：2005-01-05

    申请号：DE69821560

    申请日：1998-07-28

    Applicant: ST MICROELECTRONICS SA

    Inventor： DUTARTRE DIDIER ,  JERIER PATRICK

    IPC: C30B29/06 ,  C23C16/24 ,  C30B25/02 ,  C30B25/20 ,  H01L21/205

    Abstract: In a process for gas phase epitaxial deposition of silicon on a silicon substrate having doped zones of high arsenic concentration, self-doping of the epitaxial layer with arsenic is avoided by (a) carrying out a first thin epitaxial deposition (t5-t6) and subsequent anneal (t6-t3) under conditions and for a time such that the arsenic diffusion length is much less than the deposited layer thickness; and (b) carrying out a second epitaxial deposition (t3-t4) to achieve the desired layer thickness. Preferably, step (a) is carried out at 1100 degrees C for a time to achieve 40-60 nm thickness and step (b) is carried out at 1050 degrees C.

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