公开(公告)号：KR20120060280A

公开(公告)日：2012-06-12

申请号：KR20100121449

申请日：2010-12-01

Applicant: KOREA ELECTRONICS TELECOMM

Inventor： CHO YOUNG KYUN ,  JEON YOUNG DEUK ,  NAM JAE WON ,  KWON JONG KEE

IPC: H03M1/38

CPC classification number: H03M1/0621 ,  H03M1/38 ,  H03M2201/2233 ,  H03M2201/6107 ,  H03M2201/622

Abstract: PURPOSE: A SAR(Successive Approximation Register) ADC(Analog To Digital Converter) and an operation method thereof are provided to improve an operation speed of analog to digital conversion by optimizing latch movement. CONSTITUTION: An SAR(Successive Approximation Register) ADC(Analog To Digital Converter)(100) improves an operation speed in comparison with a general SAR ADC by using an asynchronous clock signal. The SAR ADC includes a digital conversion unit(110), an asynchronous clock generating circuit(120), and an SAR controller(130). The digital conversion unit changes an analog input voltage in response to a clock signal of the asynchronous clock generating circuit into digital signals. The asynchronous clock generating circuit generates the clock signal for controlling a sampling operation and a digital conversion operation in the digital conversion unit. The SAR controller controls the overall operation of the SAR ADC.

Abstract translation: 目的：提供SAR（逐次逼近寄存器）ADC（模数转换器）及其操作方法，通过优化锁存器移动来提高模数转换的操作速度。 构成：通过使用异步时钟信号，SAR（逐次逼近寄存器）ADC（模数转换器）（100）可以提高与通用SAR ADC相比的运行速度。 SAR ADC包括数字转换单元（110），异步时钟发生电路（120）和SAR控制器（130）。 数字转换单元响应于异步时钟产生电路的时钟信号将模拟输入电压改变成数字信号。 异步时钟产生电路产生用于控制数字转换单元中的采样操作和数字转换操作的时钟信号。 SAR控制器控制SAR ADC的整体运行。

公开(公告)号：KR1020100013713A

公开(公告)日：2010-02-10

申请号：KR1020080075344

申请日：2008-07-31

Applicant: 동명대학교산학협력단

Inventor： 박부견 ,  최윤종 ,  윤성욱

IPC: H03M1/36

CPC classification number: H03M1/0621 ,  H03M1/361 ,  H03M1/38 ,  H03M2201/2216 ,  H03M2201/6107

Abstract: PURPOSE: A method for eliminating input quantization effect is provided to obtain asymptotic stability of a system by reducing a quantization error without controlling a parameter or adding the hardware. CONSTITUTION: A control value for stabilizing a system is determined when changing a quantization level of the system input within one level(S100). A control value is added to the input of the system(S110). The control value is the integral multiple with a quantization level for maintaining the quantization level to an upper level, a lower level, and a current level.

Abstract translation: 目的：提供一种消除输入量化效应的方法，通过在不控制参数或增加硬件的情况下减少量化误差来获得系统的渐近稳定性。 构成：在一个级别中改变系统输入的量化级别时，确定稳定系统的控制值（S100）。 控制值被添加到系统的输入端（S110）。 控制值是具有用于将量化电平维持在较高电平，较低电平和当前电平的量化电平的积分倍数。

公开(公告)号：KR1020090038244A

公开(公告)日：2009-04-20

申请号：KR1020070103646

申请日：2007-10-15

Applicant: 동국대학교 산학협력단

Inventor： 송민규 ,  황상훈

IPC: H03M1/66

CPC classification number: H03M1/70 ,  H03M1/668 ,  H03M2201/6107 ,  H03M2201/932

Abstract: An adaptive control circuit for the current cell control of a digital-analog converter and the digital analog converter including the same are provided to reduce the peak noise of the current source and the vibration noise of the output signal by reducing the variance of the signal switching. A digital to analog converter comprises a controller(40), an adaptation controller(50), and an analog signal output unit(60). The adaptation controller and the analog signal output unit are included in each cell of the current cell. The controller outputs the first control signal(Vin,Vinb) for switching the MOS transistor included in the analog signal output to the adaptation controller. The adaptation controller receives the first control signal from the controller, and adjusts the variance of the first control signal, and produces the second controlling signal(vin',Vinb'), and outputs the generated second controlling signal to the analog signal output unit. The analog signal output unit outputs the analog signal according to the second controlling signal.

Abstract translation: 提供了用于数模转换器的当前单元控制的自适应控制电路和包括其的数字模拟转换器，以通过减少信号切换的方差来减小电流源的峰值噪声和输出信号的振动噪声 。 数模转换器包括控制器（40），自适应控制器（50）和模拟信号输出单元（60）。 自适应控制器和模拟信号输出单元包括在当前单元的每个单元中。 控制器输出第一控制信号（Vin，Vinb），用于切换输出到自适应控制器的模拟信号中包括的MOS晶体管。 自适应控制器从控制器接收第一控制信号，并调整第一控制信号的方差，并产生第二控制信号（vin'，Vinb'），并将产生的第二控制信号输出到模拟信号输出单元。 模拟信号输出单元根据第二控制信号输出模拟信号。

公开(公告)号：KR1020090034663A

公开(公告)日：2009-04-08

申请号：KR1020070100028

申请日：2007-10-04

Applicant: 고려대학교 산학협력단

Inventor： 김진우 ,  김무영 ,  이호규 ,  김철우

IPC: H03M1/12

CPC classification number: H03M1/186 ,  H03M1/002 ,  H03M2201/196 ,  H03M2201/6107 ,  H03M2201/622

Abstract: A method and an apparatus for converting an analog signal into a digital signal are provided to reduce the number of preamplifiers and comparators by reducing a comparison range by the resistance heat switching. A switching control unit(220) controls a switch according to an input voltage. A first comparator(230) controls a comparison range according to an output value of the switching control unit. An encoding unit(260) encodes a digital code outputted from the first comparator.

Abstract translation: 提供一种用于将模拟信号转换为数字信号的方法和装置，通过减小电阻热切换的比较范围来减少前置放大器和比较器的数量。 切换控制单元（220）根据输入电压来控制开关。 第一比较器（230）根据切换控制单元的输出值控制比较范围。 编码单元（260）对从第一比较器输出的数字码进行编码。

公开(公告)号：KR1020080086752A

公开(公告)日：2008-09-26

申请号：KR1020070028844

申请日：2007-03-23

Applicant: 인하대학교 산학협력단

Inventor： 윤광섭 ,  김판수

IPC: H03M1/12

CPC classification number: H03M1/0634 ,  H03M2201/22 ,  H03M2201/6107 ,  H03M2201/6327 ,  H03M2201/6354 ,  H03M2201/8132

Abstract: A resistor averaging circuit is provided to adjust an averaging resistor value according to an input frequency by obtaining an optimal resistance according to the input frequency and then changing the optimal resistance. A resistor averaging circuit receives a pre-amplifier load resistance(R0) and an output voltage of a pre-amplifier stage. An averaging resistor(R1) is series-connected to the resistor averaging circuit, which outputs an averaged voltage through a BOTTOM terminal. An interpolation block(2) is arranged to be adjacent to the averaging resistor. MOS(Metal Oxide Semiconductor) transistors are series-connected in the interpolation block. The averaging resistor outputs 2^(n-1) optimal resistor values according to an input frequency. Two averaging resistors are series-connected to form one averaging resistor.

Abstract translation: 提供电阻平均电路，通过根据输入频率获得最佳电阻，然后改变最佳电阻，根据输入频率调整平均电阻值。 电阻平均电路接收前置放大器负载电阻（R0）和前置放大器级的输出电压。 平均电阻（R1）串联连接到电阻平均电路，其通过BOTTOM端子输出平均电压。 插值块（2）被布置成与平均电阻器相邻。 MOS（金属氧化物半导体）晶体管串联在插值块中。 平均电阻根据输入频率输出2 ^（n-1）个最优电阻值。 两个平均电阻串联连接形成一个平均电阻。

公开(公告)号：KR1020080064294A

公开(公告)日：2008-07-09

申请号：KR1020070001033

申请日：2007-01-04

Applicant: 콘티넨탈 오토모티브 시스템 주식회사

Inventor： 장형태

IPC: H03M1/12

CPC classification number: H03M1/0607 ,  H03M1/0845 ,  H03M1/089 ,  H03M2201/6107 ,  H03M2201/615 ,  H03M2201/6327 ,  H03M2201/639

Abstract: An AD converter and a method for correcting a conversion error are provided to output an accurate AD conversion result regardless of variation of a reference voltage by implementing an error correction processing based on a fixed input voltage. A method for correcting conversion error includes the steps of: receiving an input voltage from a predetermined circuit having an AD converter(S100); performing an AD conversion based on a predetermined reference voltage and data format(S104); determining whether the reference voltage is changed or not(S106); generating an error value by comparing the input voltage with the operating measurement value of the AD conversion based on the determined result(S112); and correcting a converting error by multiplying the operating measurement value of the AD conversion by a correction value corresponding to the error value(S114).

Abstract translation: 提供AD转换器和用于校正转换误差的方法，通过实施基于固定输入电压的纠错处理，而不管参考电压的变化，输出精确的AD转换结果。 用于校正转换误差的方法包括以下步骤：从具有AD转换器的预定电路接收输入电压（S100）; 基于预定参考电压和数据格式执行AD转换（S104）; 确定参考电压是否改变（S106）; 通过基于所确定的结果将输入电压与AD转换的操作测量值进行比较来产生误差值（S112）; 以及通过将AD转换的操作测量值乘以与误差值相对应的校正值来校正转换误差（S114）。

公开(公告)号：KR1020070111163A

公开(公告)日：2007-11-21

申请号：KR1020060044183

申请日：2006-05-17

Applicant: 고려대학교 산학협력단

Inventor： 최원호 ,  김수원

IPC: H03M1/12 ,  H03K3/02

CPC classification number: H03M1/14 ,  H03K3/02 ,  H03M1/002 ,  H03M2201/6107 ,  H03M2201/76

Abstract: A programmable clock generator and a pipelined converter using the same are provided to use a clock signal having an optimum duty ratio by changing a control voltage according to power consumption, thereby minimizing the power consumption. A first programmable inverter(410) is connected to a reference clock at both input terminals, and varies a period in which the reference clock is inverted. An inverter(420) is connected to the reference clock to inverter the reference clock. A second programmable inverter(430) is connected to an input terminal of the inverter to vary a period in which the signal of the input terminal is inverted. First and second latch circuits(440,450) have set inputs connected to the reference clock and the inverter and reset inputs connected to the output of the first and the second programmable inverters, respectively.

Abstract translation: 提供了一种可编程时钟发生器和使用该可编程时钟发生器的流水线转换器，以通过根据功耗改变控制电压来使用具有最佳占空比的时钟信号，从而最小化功耗。 第一可编程反相器（410）在两个输入端子处连接到参考时钟，并且改变参考时钟反相的周期。 逆变器（420）连接到参考时钟以使参考时钟反相。 第二可编程逆变器（430）连接到逆变器的输入端，以改变输入端的信号反转的周期。 第一和第二锁存电路（440,450）分别具有连接到参考时钟和反相器的设置输入和连接到第一和第二可编程反相器的输出的复位输入。

公开(公告)号：KR1020070082354A

公开(公告)日：2007-08-21

申请号：KR1020060015081

申请日：2006-02-16

Applicant: 삼성전자주식회사

Inventor： 송태익 ,  신용원 ,  임종한 ,  이종훈

IPC: H03M1/66 ,  H04B1/40

CPC classification number: H03M1/70 ,  H03M2201/196 ,  H03M2201/6107 ,  H03M2201/62

Abstract: An apparatus and a method for controlling a dynamic range of a DAC(Digital to Analog Converter) input signal are provided to optimize the performance of a DAC by actively controlling the DAC input signal according to the number of channels and operation scenarios. Diffused signals including a plurality of channel signals having predetermined digital gain values outputted by a PN diffuser(202) pass through a gain normalizer(204) before transmission to an LPF(Low Pass Filter)(206). The gain normalizer(204) normalizes the diffused signals of N + m bits with normalization factors in accordance with an input operation range of a DAC(210) to output normalized signals of N bits. The PN diffuser(202) generates the diffused signals of larger bits that is N+m bits by using the gain normalizer(204). The output of the gain normalizer(204) is filtered by the LPF(206) to be transmitted to an interpolator(208). The interpolator(208) interpolates the signals transmitted from the LPF(206) in consideration of the input operation range of the DAC(210) to provide the interpolated signals to the DAC(210). The DAC(210) converts the interpolated signals into analog signals and outputs the converted signals.

Abstract translation: 提供了一种用于控制DAC（数模转换器）输入信号的动态范围的装置和方法，以通过根据信道数量和操作情况主动地控制DAC输入信号来优化DAC的性能。 包括具有由PN扩散器（202）输出的预定数字增益值的多个信道信号的扩散信号在传输到LPF（低通滤波器）（206）之前经过增益归一化器（204）。 增益归一化器（204）根据DAC（210）的输入操作范围使归一化因子对N + m位的扩散信号进行归一化，以输出N位的归一化信号。 PN漫射器（202）通过使用增益归一化器（204）产生N + m比特的较大比特的扩散信号。 增益归一化器（204）的输出由LPF（206）滤波以被发送到内插器（208）。 考虑到DAC（210）的输入操作范围，插值器（208）内插从LPF（206）发送的信号，以将内插信号提供给DAC（210）。 DAC（210）将内插信号转换为模拟信号并输出​​转换后的信号。

公开(公告)号：KR1020060068397A

公开(公告)日：2006-06-21

申请号：KR1020040107070

申请日：2004-12-16

Applicant: 한국과학기술원

Inventor： 김선영 ,  유회준

IPC: H03M3/02

CPC classification number: H03M3/352 ,  H03M3/32 ,  H03M3/396 ,  H03M2201/6107

Abstract: 본 발명은 적응형 시그마 델타 변조기에 관한 것으로서, 입력신호의 크기를 감지하고 이를 변수화하여 변조기의 시스템 클럭 주파수와 적분기의 차수를 동적으로 제어함으로써 다양한 신호 대 잡음비(SNR)를 제공함으로써 임의의 입력에 대한 과도한 변조기의 성능을 완화시켜 입력신호에 적응하여 최적화된 성능을 제공하며 동시에 전력소모를 줄일 수 있는 이점이 있다.
적응형, 시그마 델타, 가변차수, 가변클럭, 신호대 잡음비, SNR, 소모전력

公开(公告)号：KR1020020050442A

公开(公告)日：2002-06-27

申请号：KR1020000079591

申请日：2000-12-21

Applicant: 엘지디스플레이 주식회사

Inventor： 신천기

IPC: H03M1/46

CPC classification number: H03M1/34 ,  H03M2201/6107 ,  H03M2201/622

Abstract: PURPOSE: An A/D(Analog/Digital) converter circuit and a method for converting an analog signal into a digital signal are provided, which reduces a conversion time and improves a conversion accuracy, by measuring only bits of high error among the whole bits according as converting the analog signal into the digital signal. CONSTITUTION: A MUX part(21) selects and outputs an inputted analog signal, and a comparator part(22) compares an output of the above MUX part with a reference signal. A microprocessor(23) outputs a digital signal of plural bits where only bits sensitive to noise are converted among digital signals of plural bits corresponding to the analog signal inputted according to the comparison result of the comparator part. And a digital/analog converter part(24) converts the digital signal being output from the microprocessor into an analog signal and then transfers it as a reference signal of the comparator part.

Abstract translation: 目的：提供A / D（模拟/数字）转换器电路和将模拟信号转换为数字信号的方法，通过仅测量整个位中的高误差位，减少转换时间并提高转换精度 根据将模拟信号转换为数字信号。 构成：MUX部分（21）选择并输出输入的模拟信号，比较器部分（22）将上述MUX部分的输出与参考信号进行比较。 微处理器（23）根据比较器部分的比较结果输出多个比特的数字信号，其中只有对噪声敏感的位被转换成与根据输入的模拟信号相对应的多个位的数字信号。 并且数字/模拟转换器部分（24）将从微处理器输出的数字信号转换为模拟信号，然后将其作为比较器部分的参考信号传送。