公开(公告)号：KR1020050019477A

公开(公告)日：2005-03-03

申请号：KR1020030057274

申请日：2003-08-19

Applicant: 한국전자통신연구원

Inventor： 박종문 ,  박건식 ,  유성욱 ,  윤용선 ,  김상기 ,  김보우 ,  구진근

IPC: H01L21/335

Abstract: PURPOSE: A method for fabricating T gate in a compound semiconductor device is provided to reduce number of a manufacturing process by once coating one kind of resist. CONSTITUTION: A dielectric film(52) is formed on a semiconductor substrate(50). A resist layer is formed on the dielectric film. A resist layer pattern(54a) is formed by patterning firstly the resist layer. The compound semiconductor substrate is exposed by a first opening(62) that is formed by etching the dielectric film with the resist layer pattern as a mask. A second opening that is larger than the first opening is formed by patterning secondly the resist layer pattern. A metal film buries the first opening, simultaneously the metal film is also formed at the lower portion of the second opening and on the whole surface of the compound semiconductor substrate that the resist layer pattern is formed thereon. A T-type gate showing a leg-type in the first opening and a body-type on the dielectric film is formed by removing the resist layer pattern.

Abstract translation: 目的：提供一种在化合物半导体器件中制造T栅的方法，以通过一次涂覆一种抗蚀剂来减少制造工艺的数量。 构成：在半导体衬底（50）上形成电介质膜（52）。 在电介质膜上形成抗蚀剂层。 通过首先形成抗蚀剂层形成抗蚀剂层图案（54a）。 化合物半导体衬底通过用抗蚀剂层图案作为掩模蚀刻电介质膜而形成的第一开口（62）暴露。 大于第一开口的第二开口通过二次图案化形成抗蚀剂层图案。 金属膜掩埋第一开口，同时金属膜也形成在第二开口的下部和化合物半导体衬底的形成有抗蚀剂层图案的整个表面上。 通过去除抗蚀剂层图案，形成在第一开口中显示腿型的T型栅极和电介质膜上的体型。

公开(公告)号：KR100448889B1

公开(公告)日：2004-09-18

申请号：KR1020020072960

申请日：2002-11-22

Applicant: 한국전자통신연구원

Inventor： 이대우 ,  김상기 ,  구진근 ,  유병곤 ,  김종대

IPC: H01L27/12

Abstract: PURPOSE: A method for fabricating a power IC using an SOI substrate is provided to enhance resolution of a display unit by improving and optimizing the accuracy of a fabrication process. CONSTITUTION: A first trench(34a) and a second trench(34b) are formed by etching partially an SOI substrate(31). A well of an LDMOS element, a floating region, and a well of a CMOS element are formed within the SOI substrate. The first and the second field oxide layer(42a,42b) are buried into the first and the second trenches. A third field oxide layer(42c) is formed on the floating region. A thick gate insulating layer(45a) of the LDMOS element and a thin gate insulating layer(45b) of the CMOS element are formed thereon. A gate electrode(46a) of the LDMOS element and gate electrodes(46b,46c) of the CMOS element are formed simultaneously. An LDD region of the LDMOS element and an LDD region of the CMOS element are formed within the SOI substrate of both sides of the gate electrodes. Spacers are formed on sidewalls of the gate electrodes, respectively. A source region of the LDMOS element and a source/drain region of the CMOS element are formed, respectively.

Abstract translation: 目的：提供一种使用SOI衬底制造功率IC的方法，以通过改善和优化制造工艺的精度来提高显示单元的分辨率。 构成：通过部分蚀刻SOI衬底（31）形成第一沟槽（34a）和第二沟槽（34b）。 在SOI衬底内形成LDMOS元件的阱，浮置区域和CMOS元件的阱。 第一和第二场氧化物层（42a，42b）被埋入第一和第二沟槽中。 第三场氧化层（42c）形成在浮置区上。 在其上形成LDMOS元件的厚栅绝缘层（45a）和CMOS元件的薄栅绝缘层（45b）。 同时形成LDMOS元件的栅电极（46a）和CMOS元件的栅电极（46b，46c）。 LDMOS元件的LDD区域和CMOS元件的LDD区域形成在栅电极两侧的SOI衬底内。 间隔物分别形成在栅电极的侧壁上。 分别形成LDMOS元件的源极区域和CMOS元件的源极/漏极区域。

公开(公告)号：KR100438892B1

公开(公告)日：2004-07-02

申请号：KR1020010082476

申请日：2001-12-21

Applicant: 한국전자통신연구원

Inventor： 구진근 ,  김상기 ,  박일용 ,  김종대

IPC: H01L27/02

Abstract: PURPOSE: An one chip type thin film inductor and a method for manufacturing the same are provided to be capable of reducing the size and weight of a chip module package by forming an IC(Integrated Circuit) and the thin film inductor on the same semiconductor substrate. CONSTITUTION: The first and second well region(221,241) are formed in a semiconductor substrate(200). The first and second MOS(Metal Oxide Semiconductor) transistor(pMOS,nMOS) are formed on the first and second well region, respectively. A plurality of metal layer patterns(202,204) are electrically connected between the first and second MOS transistor and impurity regions(222,242). A protecting isolation layer(205) is located on the resultant structure for separating the metal layer patterns. A lower core layer pattern(262) is formed on the predetermined portion of the protecting isolation layer. The first polyimide layer(261), a metal coil layer(264), the second polyimide layer(263), an upper core layer pattern(269), and the third polyimide layer(267) are sequentially formed on the resultant structure.

Abstract translation: 目的：通过在同一半导体衬底上形成IC（集成电路）和薄膜电感器，提供了一种单片型薄膜电感器及其制造方法，以便能够减小芯片模块封装的尺寸和重量 。 构成：第一和第二阱区（221,241）形成在半导体衬底（200）中。 第一和第二MOS（金属氧化物半导体）晶体管（pMOS，nMOS）分别形成在第一和第二阱区上。 多个金属层图案（202,204）电连接在第一和第二MOS晶体管与杂质区（222,242）之间。 保护隔离层（205）位于所得结构上以分离金属层图案。 在保护隔离层的预定部分上形成下芯层图案（262）。 在所得到的结构上依次形成第一聚酰亚胺层（261），金属线圈层（264），第二聚酰亚胺层（263），上芯层图案（269）和第三聚酰亚胺层（267）。

公开(公告)号：KR1020040045512A

公开(公告)日：2004-06-02

申请号：KR1020020073313

申请日：2002-11-23

Applicant: 한국전자통신연구원

Inventor： 윤성민 ,  이남열 ,  유인규 ,  김귀동 ,  류상욱 ,  조성목 ,  신웅철 ,  최규정 ,  유병곤 ,  구진근

IPC: H01L27/105

Abstract: PURPOSE: A gate stack of a ferroelectric memory FET(Field Effect Transistor) and a manufacturing method thereof are provided to be capable of optimizing the electrical characteristics of the device. CONSTITUTION: A gate stack(25) of a ferroelectric memory FET is provided with a semiconductor substrate(11) and a diffusion barrier(19) formed on the semiconductor substrate. At this time, the diffusion barrier is completed by sequentially forming a silicon oxide layer(13), a silicon nitride layer(15), and a silicon oxide layer(17). The gate stack further includes a Bi-La-Ti-O ferroelectric layer(21) formed on the diffusion barrier and an upper electrode(23) formed on the ferroelectric layer. Preferably, a (BixLa1-x)4Ti3O12 layer is used as the ferroelectric layer.

Abstract translation: 目的：提供铁电存储FET（场效应晶体管）的栅极叠层及其制造方法，能够优化器件的电气特性。 构成：铁电存储器FET的栅极堆叠（25）设置有形成在半导体衬底上的半导体衬底（11）和扩散阻挡层（19）。 此时，通过依次形成氧化硅层（13），氮化硅层（15）和氧化硅层（17）来完成扩散阻挡层。 栅堆叠还包括形成在扩散阻挡层上的Bi-La-Ti-O铁电层（21）和形成在强电介质层上的上电极（23）。 优选使用（BixLa1-x）4Ti3O12层作为铁电体层。

公开(公告)号：KR1020040044785A

公开(公告)日：2004-05-31

申请号：KR1020020072960

申请日：2002-11-22

Applicant: 한국전자통신연구원

Inventor： 이대우 ,  김상기 ,  구진근 ,  유병곤 ,  김종대

IPC: H01L27/12

Abstract: PURPOSE: A method for fabricating a power IC using an SOI substrate is provided to enhance resolution of a display unit by improving and optimizing the accuracy of a fabrication process. CONSTITUTION: A first trench(34a) and a second trench(34b) are formed by etching partially an SOI substrate(31). A well of an LDMOS element, a floating region, and a well of a CMOS element are formed within the SOI substrate. The first and the second field oxide layer(42a,42b) are buried into the first and the second trenches. A third field oxide layer(42c) is formed on the floating region. A thick gate insulating layer(45a) of the LDMOS element and a thin gate insulating layer(45b) of the CMOS element are formed thereon. A gate electrode(46a) of the LDMOS element and gate electrodes(46b,46c) of the CMOS element are formed simultaneously. An LDD region of the LDMOS element and an LDD region of the CMOS element are formed within the SOI substrate of both sides of the gate electrodes. Spacers are formed on sidewalls of the gate electrodes, respectively. A source region of the LDMOS element and a source/drain region of the CMOS element are formed, respectively.

Abstract translation: 目的：提供一种使用SOI衬底制造功率IC的方法，通过改进和优化制造工艺的精度来提高显示单元的分辨率。 构成：通过部分蚀刻SOI衬底（31）形成第一沟槽（34a）和第二沟槽（34b）。 在SOI衬底内形成有LDMOS元件，浮动区和CMOS元件的阱的阱。 第一和第二场氧化物层（42a，42b）被埋入第一和第二沟槽中。 在浮动区域上形成第三场氧化物层（42c）。 在其上形成LDMOS元件的厚栅极绝缘层（45a）和CMOS元件的薄栅极绝缘层（45b）。 同时形成LDMOS元件的栅极（46a）和CMOS元件的栅电极（46b，46c）。 在栅电极的两侧的SOI衬底内形成LDMOS元件的LDD区域和CMOS元件的LDD区域。 隔板分别形成在栅电极的侧壁上。 分别形成LDMOS元件的源极区域和CMOS元件的源极/漏极区域。

公开(公告)号：KR1020040019484A

公开(公告)日：2004-03-06

申请号：KR1020020051029

申请日：2002-08-28

Applicant: 한국전자통신연구원

Inventor： 양일석 ,  김종대 ,  노태문 ,  구진근 ,  이대우 ,  김상기 ,  박일용

IPC: H03K19/00

CPC classification number: H03K19/0016

Abstract: PURPOSE: An input/output port circuit is provided, which is driven by high supply voltage and low supply voltage at the same time, and reduces power consumption by selectivly driving the input/output port circuit. CONSTITUTION: A signal register(22) stores output signals, and an input/output register(23) stores an input/output control signal determining an input/output direction. A power supply switch circuit(21) supplies a high voltage or a low voltage selectively according to a control signal. A signal control circuit(24) determines a direction of a signal according to a value of the signal register and a value of the input/output register. An output control circuit(25) is driven according to a value of the control register and an output of the signal control circuit. And an output driver circuit(26) outputs the low voltage and the high voltage or a ground value according to outputs of the signal control circuit and the output control circuit. The input/output port circuit comprises a number of output control registers(27).

Abstract translation: 目的：提供输入/输出端口电路，同时由高电源电压和低电源电压驱动，并通过选择性驱动输入/输出端口电路降低功耗。 构成：信号寄存器（22）存储输出信号，输入/输出寄存器（23）存储确定输入/输出方向的输入/输出控制信号。 电源开关电路（21）根据控制信号选择性地提供高电压或低电压。 信号控制电路（24）根据信号寄存器的值和输入/输出寄存器的值确定信号的方向。 根据控制寄存器的值和信号控制电路的输出来驱动输出控制电路（25）。 并且输出驱动电路（26）根据信号控制电路和输出控制电路的输出输出低电压和高电压或接地值。 输入/输出端口电路包括多个输出控制寄存器（27）。

公开(公告)号：KR100417006B1

公开(公告)日：2004-02-05

申请号：KR1020010066228

申请日：2001-10-26

Applicant: 한국전자통신연구원

Inventor： 양일석 ,  구진근 ,  이대우 ,  김상기 ,  김종대 ,  노태문 ,  박일용

IPC: H02M3/28

Abstract: PURPOSE: A multi-output DC-DC converter is provided to be capable of outputting a multi-level voltage using one embedded inductor having a plurality of output taps. CONSTITUTION: An inductor part(300) is supplied with an input voltage and has a plurality of output taps which are spaced apart from each other. The first switching unit(230) consists of a plurality of transistors cascaded between each output tap of the inductor part and a common node and controlled by corresponding control signals. The second switching unit(210) is connected between the common node and the output terminal and is controlled by the control signal. The third switching unit(220) consists of a plurality of transistors which are connected in parallel between the common node and a ground voltage and are selectively operated according to corresponding control signals.

Abstract translation: 目的：提供一种多输出DC-DC转换器，其能够使用具有多个输出抽头的一个嵌入式电感器来输出多电平电压。 构成：电感器部件（300）被提供有输入电压并且具有彼此间隔开的多个输出抽头。 第一开关单元（230）由级联在电感器部分的每个输出抽头和公共节点之间的多个晶体管构成，并由相应的控制信号控制。 第二开关单元（210）连接在公共节点和输出端之间并由控制信号控制。 第三开关单元（220）包括并联连接在公共节点和地电压之间的多个晶体管，并且根据相应的控制信号选择性地操作。

公开(公告)号：KR100400079B1

公开(公告)日：2003-09-29

申请号：KR1020010062350

申请日：2001-10-10

Applicant: 한국전자통신연구원

Inventor： 박일용 ,  김종대 ,  김상기 ,  구진근 ,  이대우 ,  노태문 ,  양일석

IPC: H01L29/78

CPC classification number: H01L29/7813 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/7802

Abstract: A method for fabricating a power semiconductor device having a trench gate structure is provided. An epitaxial layer of a first conductivity type having a low concentration and a body region of a second conductivity type are sequentially formed on a semiconductor substrate of the first conductivity type having a high concentration. An oxide layer pattern is formed on the body region. A first trench is formed using the oxide layer pattern as an etching mask to perforate a predetermined portion of the body region having a first thickness. A body contact region of the second conductivity type having a high concentration is formed to surround the first trench by impurity ion implantation using the oxide layer pattern as an ion implantation mask. First spacer layers are formed to cover the sidewalls of the first trench and the sidewalls of the oxide layer pattern. A second trench is formed using the oxide layer pattern and the first spacer layers as etching masks to perforate a predetermined portion of the body region having a second thickness greater than the first thickness. A source region of the first conductivity type having a high concentration is formed to surround the second trench by impurity ion implantation using the oxide layer pattern and the first spacer layers as ion implantation masks. Second spacer layers are formed to cover the sidewalls of the second trench and the sidewalls of the first spacer layers. A third trench is formed to a predetermined depth of the epitaxial layer using the oxide layer pattern, the first spacer layers, and the second spacer layers as etching masks. A gate insulating layer is formed in the third trench. A gate conductive pattern is formed in the gate insulating layer. An oxide layer is formed on the gate conductive layer pattern. The first and second spacer layers are removed. A first metal electrode layer is formed to be electrically connected to the source region and the body contact region. A second metal electrode layer is formed to be electrically connected to the gate conductive layer pattern. A third metal electrode layer is formed to be electrically connected to the semiconductor substrate.

Abstract translation: 提供了一种用于制造具有沟槽栅极结构的功率半导体器件的方法。 在具有高浓度的第一导电类型的半导体衬底上顺序地形成具有低浓度的第一导电类型的外延层和具有第二导电类型的本体区域。 在体区上形成氧化层图案。 使用氧化物层图案作为蚀刻掩模来形成第一沟槽，以穿透具有第一厚度的本体区域的预定部分。 使用氧化物层图案作为离子注入掩模，通过杂质离子注入围绕第一沟槽形成具有高浓度的第二导电类型的体接触区域。 形成第一间隔层以覆盖第一沟槽的侧壁和氧化物层图案的侧壁。 使用氧化物层图案和第一间隔物层作为蚀刻掩模来形成第二沟槽，以穿透具有比第一厚度大的第二厚度的本体区域的预定部分。 通过使用氧化物层图案和第一间隔层作为离子注入掩模的杂质离子注入来形成具有高浓度的第一导电类型的源极区域以围绕第二沟槽。 形成第二间隔层以覆盖第二沟槽的侧壁和第一间隔层的侧壁。 使用氧化物层图案，第一间隔物层和第二间隔物层作为蚀刻掩模，将第三沟槽形成至外延层的预定深度。 栅极绝缘层形成在第三沟槽中。 栅极导电图案形成在栅极绝缘层中。 在栅极导电层图案上形成氧化物层。 第一和第二间隔层被去除。 第一金属电极层形成为电连接到源极区和体接触区。 第二金属电极层被形成为与栅极导电层图案电连接。 形成第三金属电极层以电连接到半导体衬底。

公开(公告)号：KR1020030054758A

公开(公告)日：2003-07-02

申请号：KR1020010085165

申请日：2001-12-26

Applicant: 한국전자통신연구원

Inventor： 노태문 ,  이대우 ,  양일석 ,  박일용 ,  김상기 ,  구진근 ,  김종대

IPC: H01L21/76

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: PURPOSE: A method for fabricating a power IC is provided to reduce an isolation area by forming a nitride layer between a trench oxide layer and a polysilicon layer or performing a trench isolation process using the nitride layer and the polysilicon instead of the trench oxide layer. CONSTITUTION: An oxide layer and a photoresist layer are sequentially on a silicon layer(102). The photoresist layer is patterned by using a trench mask. The oxide layer is patterned by using the patterned photoresist layer as a mask. The remaining photoresist is removed therefrom. The trench is etched by using the patterned oxide layer as the mask and a trench is formed thereby. A nitride layer(134) is formed on an upper surface of the resultant including the trench. The trench is buried by depositing a polysilicon thereon. An isolation layer is formed by removing the polysilicon and the nitride layer.

Abstract translation: 目的：提供一种用于制造功率IC的方法，通过在沟槽氧化物层和多晶硅层之间形成氮化物层或者使用氮化物层和多晶硅代替沟槽氧化物层来执行沟槽隔离工艺来减小隔离区域。 构成：氧化物层和光致抗蚀剂层顺序地在硅层（102）上。 通过使用沟槽掩模来对抗蚀剂层进行构图。 通过使用图案化的光致抗蚀剂层作为掩模来对氧化物层进行构图。 从中除去剩余的光致抗蚀剂。 通过使用图案化氧化物层作为掩模来蚀刻沟槽，由此形成沟槽。 在包括沟槽的结果的上表面上形成氮化物层（134）。 通过在其上沉积多晶硅来掩埋沟槽。 通过去除多晶硅和氮化物层形成隔离层。

公开(公告)号：KR100388063B1

公开(公告)日：2003-06-27

申请号：KR1020000078264

申请日：2000-12-19

Applicant: 한국전자통신연구원

Inventor： 노태문 ,  김종대 ,  김상기 ,  이대우 ,  구진근 ,  조경익

IPC: H01L27/04

Abstract: PURPOSE: A method for fabricating a power integrated circuit is provided to remarkably reduce a high temperature annealing process for fabricating the power integrated circuit, by mixing a non-reduced surface field(RESURF) n-lateral double diffused metal oxide semiconductor(LDMOS) transistor and a RESURF p-LDMOS transistor. CONSTITUTION: The power integrated circuit includes the RESURF LDMOS transistor using a silicon-on-insulator, the non-RESURF LDMOS transistor of an opposite type to the RESURF LDMOS transistor and a logic complementary metal oxide semiconductor(CMOS). The regions where the logic CMOS as a low voltage device and an LDMOS transistor as a high power device are fabricated are doped with the same impurity type in a silicon substrate.

Abstract translation: 目的：提供一种用于制造功率集成电路的方法，以通过混合非减小表面场（RESURF）n型横向双扩散金属氧化物半导体（LDMOS）晶体管来显着减少用于制造功率集成电路的高温退火工艺 和RESURF p-LDMOS晶体管。 构成：功率集成电路包括使用绝缘体上硅的RESURF LDMOS晶体管，与RESURF LDMOS晶体管和逻辑互补金属氧化物半导体（CMOS）相反类型的非RESURF LDMOS晶体管。 作为低电压器件的逻辑CMOS和作为高功率器件的LDMOS晶体管被制造的区域在硅衬底中掺杂有相同的杂质类型。