公开(公告)号：DE102014110655A1

公开(公告)日：2015-02-05

申请号：DE102014110655

申请日：2014-07-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BIRNER ALBERT ,  BRECH HELMUT ,  ZIGLDRUM MATTHIAS

IPC: H01L23/488 ,  H01L21/60 ,  H01L23/50 ,  H01L23/522

Abstract: Gemäß einer Ausführungsform der vorliegenden Erfindung weist ein Halbleiterbauelement eine erste Bondkontaktierungsinsel auf, die an einer ersten Seite eines Substrats positioniert ist. Die erste Bondkontaktierungsinsel weist eine erste Vielzahl von Kontaktierungsinselsegmenten auf. Mindestens ein Kontaktierungsinselsegment der ersten Vielzahl von Kontaktierungsinselsegmenten ist elektrisch von den übrigen Kontaktierungsinselsegmenten der ersten Vielzahl von Kontaktierungsinselsegmenten isoliert.

公开(公告)号：DE102013211553A1

公开(公告)日：2013-12-24

申请号：DE102013211553

申请日：2013-06-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BIRNER ALBERT ,  HERZIG TOBIAS

IPC: H01L21/66 ,  H01L21/768 ,  H01L23/52 ,  H01L23/544

Abstract: Nach einer Ausführungsform der vorliegenden Erfindung beinhaltet ein Verfahren zum Bilden eines elektronischen Bauelements Bilden einer ersten Öffnung und einer zweiten Öffnung in einem Werkstück. Die erste Öffnung ist tiefer als die zweite Öffnung. Das Verfahren beinhaltet ferner Bilden eines Füllmaterials innerhalb der ersten Öffnung, um einen Teil einer Durchkontaktierung zu bilden, und Bilden des Füllmaterials innerhalb der zweiten Öffnung.

公开(公告)号：DE102008002653A1

公开(公告)日：2009-02-05

申请号：DE102008002653

申请日：2008-06-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BIRNER ALBERT ,  CHEN QIANG

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/762

公开(公告)号：DE102005002675B4

公开(公告)日：2007-02-22

申请号：DE102005002675

申请日：2005-01-20

Applicant: INFINEON TECHNOLOGIES AG

Inventor： WELLHAUSEN UWE ,  HOLLATZ MARK ,  DAS ARABINDA ,  KLIPP ANDREAS ,  SPERLICH HANS-PETER ,  BIRNER ALBERT ,  HEIDEMEYER HENRY

IPC: H01L21/314 ,  H01L21/762

Abstract: The method involves pretreating a semiconductor structure before superimposing the spin-on layer to obtain a plane surface of the spin-on layer. A liner layer is superimposed on a semiconductor structure before the superimposition of the spin-on-layer. The semiconductor structure supports a planar superimposition of the spin-on layer on it. An oxide layer is superimposed as a liner layer, whose thickness is greater than 2.0 mm. An independent claim is also included for a semiconductor structure, in particular a semiconductor wafer with a substrate.

公开(公告)号：DE10326805B4

公开(公告)日：2007-02-15

申请号：DE10326805

申请日：2003-06-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLDBACH MATTHIAS ,  MIKOLAJICK THOMAS ,  BIRNER ALBERT

IPC: H01L21/8247 ,  H01L21/28 ,  H01L21/336 ,  H01L29/423 ,  H01L29/788

Abstract: Silicon nanocrystals are applied as storage layer ( 6 ) and removed using spacer elements ( 11 ) laterally with respect to the gate electrode ( 5 ). By means of an implantation of dopant, source/drain regions ( 2 ) are fabricated in a self-aligned manner with respect to the storage layer ( 6 ). The portions of the storage layer ( 6 ) are interrupted by the gate electrode ( 5 ) and the gate dielectric ( 4 ), so that a central portion of the channel region ( 3 ) is not covered by the storage layer ( 6 ). This memory cell is suitable as a multi-bit flash memory cell in a virtual ground architecture.

公开(公告)号：DE102005037566A1

公开(公告)日：2007-02-15

申请号：DE102005037566

申请日：2005-08-09

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BIRNER ALBERT ,  WEBER ANDREAS ,  WEIS ROLF

IPC: H01L21/336 ,  H01L21/8247

Abstract: In a method for fabricating a semiconductor structure a semiconductor substrate comprising an active region with an uncovered top side is provided, at least one STI trench adjoining the active region is formed, and an STI divot is formed in the insulating filling. The at least one STI trench comprises an insulating filling extending to above the top side of the active region and the divot adjoins the active region and uncovers an edge of the uncovered top side of the active region. A hydrogen termination of the uncovered top side of the active region is formed and a heat treatment in a hydrogen atmosphere is carried out in order to form a rounding from the edge of the active region in such a way that the top side of the active region continuously merges into the STI divot.

公开(公告)号：DE102005005327A1

公开(公告)日：2005-12-15

申请号：DE102005005327

申请日：2005-02-04

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BIRNER ALBERT ,  GOLDBACH MATTHIAS

IPC: H01L21/335 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/085 ,  H01L29/745

Abstract: In order to insulate active areas of n-type FETs and p-type FETs, insulator structures which due to production exert a tensile stress or a compressive stress on the respectively neighboring active areas, and which stress them accordingly, are provided in the semiconductor substrate in addition to the active areas formed by sections of a semiconductor substrate. The insulator structures are respectively established on a base section by which a tensile stress is induced in adjacent active areas. Insulator structures respectively next to a p-type FET are selectively provided with additional buffer layers by which, due to production, a compressive stress is induced in adjacent structures. The charge carrier mobility is increased both for electrons I n the channel regions of the n-type FETs and for holes in the channel regions of the p-type FETs, and the functionality is improved both for the n-type FETs and for the p-type FETs.

公开(公告)号：DE10321496A1

公开(公告)日：2004-12-16

申请号：DE10321496

申请日：2003-05-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GOLDBACH MATTHIAS ,  HECHT THOMAS ,  BIRNER ALBERT ,  KUDELKA STEPHAN

IPC: H01L21/02 ,  H01L21/8242 ,  H01L27/08

Abstract: The production of a trench capacitor comprises forming a trench (10) in a semiconductor substrate (1) using a hard mask (5), partially masking the upper trench region using a masking layer on the substrate, forming an insulating collar (25) on the substrate outside of the trench region, removing the collar on the substrate in the lower trench region using a mask (30), forming a capacitor dielectric (50) on the exposed substrate in the lower trench region, forming a first insulating filler (60) in the trench up to the collar in the lower and middle trench region below the masked upper trench region, selectively removing the masking layer on the upper trench region, and forming a trench contact made from a second conducting filler (70) on the first conducting filler in the trench below the upper side of the collar to contact a connecting region (KB).

公开(公告)号：DE10321466A1

公开(公告)日：2004-12-16

申请号：DE10321466

申请日：2003-05-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SEIDL HARALD ,  MANGER DIRK ,  GOLDBACH MATTHIAS ,  BIRNER ALBERT ,  SLESAZECK STEFAN

IPC: H01L21/8242 ,  H01L27/108 ,  H01L29/94

Abstract: A trench storage capacitor includes a buried plate that is lengthened by a doped silicon layer to right over the collar insulating layer. The conductor layer of the trench storage capacitor is preferably applied to a "buried" collar insulating layer and masked with the aid of a protective layer fabricated by ALD. In an exemplary embodiment, the conductor layer is composed of amorphous silicon, which is used as an HSG layer in a lower trench region.

公开(公告)号：DE10255866A1

公开(公告)日：2004-06-17

申请号：DE10255866

申请日：2002-11-29

Applicant: INFINEON TECHNOLOGIES AG

Inventor： LUETZEN JOERN ,  BIRNER ALBERT ,  KUDELKA STEPHAN ,  TEWS HELMUT ,  WEIS ROLF

IPC: H01L21/306 ,  H01L21/302 ,  H01L21/308 ,  H01L21/461 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/04

Abstract: A process for increasing the structural density (thickness, sic) and/or storage capacity of structures introduced into a semiconductor wafer (1) by marking (2) in the rupture direction, where the structures by means of a light exposure device and a mask (3) are formed on the wafer. Before formation of the structures the wafer is turned by 45 deg in its plane and is given a marking in a new direction parallel to a (100) crystal orientation. A process for increasing the structural size (density, sic) of main structures (MS) formed in the bulk of a SS by an etching process, in which main structures on one surface of the SS are exchanged in a surface section of the SS by secondary structures arranged in a surface screen (14) and directed with longitudinal and transverse extension parallel to the x and y axes of the surface screen where before etching the longitudinal and transverse extensions of the main structures are twisted relative to the x and y axes of surface screen so that the section of the SS below the secondary MS main structures is made completely available for formation of further MS by means of a further etching process. Independent claims are included for: (1) a structure in a SS comprising a drain with a limiting upper section at the surface of the SS of plan view surface profile with longitudinal sides parallel to the (100) crystal orientation and with rectangular profile in a lower section below an etch resistant protective layer with longitudinal sides parallel to the (110) crystal orientation; (2) an arrangement of structures in which the thickness of the intermediate walls between adjacent structures in the SS is of the order of 100 nm; (3) a process for reduction of leakage current in a selection transistor and a DRAM-cell with storage capacity, where DRAM = dynamic random access memory, with processing of a semiconductor wafer having a DRAM-cell; (4) a DRAM-cell obtained as above and having storage capacity.