公开(公告)号：KR100817090B1

公开(公告)日：2008-03-26

申请号：KR1020070020576

申请日：2007-02-28

Applicant: 삼성전자주식회사

Inventor： 김채령 ,  홍창기 ,  윤보언 ,  신성호 ,  권병효

IPC: H01L21/28

CPC classification number: H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/31144 ,  H01L21/7688 ,  Y10S438/947

Abstract: A method for fabricating a semiconductor device is provided to form high-density second contact plugs of fine patterns by using first contact mask layers and second contact mask layers self-aligned with the first contact mask layers. An interlayer dielectric(110) is formed on a semiconductor substrate(105) in which first and second regions are confined. First contact plugs(115c) are formed on a part of the second region, filling a plurality of first contact holes penetrating the interlayer dielectric. A plurality of first contact mask layers(115a) are formed on the interlayer dielectric in the first region, and a plurality of first dummy mask layers(115b) are formed on the interlayer dielectric in the second region. A plurality of second contact mask layers(135a) are formed on the interlayer dielectric, disposed between adjacent two of the plurality of first contact mask layers. A plurality of second dummy mask layers(135b) are formed on the interlayer dielectric, disposed between adjacent two of the plurality of first dummy mask layers. By using as an etch protection layer the plurality of first contact mask layers and the plurality of second contact mask layers, the interlayer dielectric is etched to form a plurality of second contact holes penetrating the interlayer dielectric on the first region. The plurality of first contact mask layer and the plurality of first dummy mask layers can be formed simultaneously.

Abstract translation: 提供一种制造半导体器件的方法，通过使用与第一接触掩模层自对准的第一接触掩模层和第二接触掩模层来形成精细图案的高密度第二接触塞。 在第一和第二区域被限制的半导体衬底（105）上形成层间电介质（110）。 第一接触塞（115c）形成在第二区域的一部分上，填充穿过层间电介质的多个第一接触孔。 在第一区域中的层间电介质上形成多个第一接触掩模层（115a），并且在第二区域中的层间电介质上形成多个第一伪掩模层（115b）。 多个第二接触掩模层（135a）形成在层间电介质上，设置在多个第一接触掩模层的相邻两个之间。 多个第二虚设掩模层（135b）形成在层间电介质上，设置在多个第一伪掩模层中相邻的两个之间。 通过使用多个第一接触掩模层和多个第二接触掩模层作为蚀刻保护层，蚀刻层间电介质以形成穿过第一区域上的层间电介质的多个第二接触孔。 多个第一接触掩模层和多个第一伪掩模层可以同时形成。

公开(公告)号：KR1020080017155A

公开(公告)日：2008-02-26

申请号：KR1020060078837

申请日：2006-08-21

Applicant: 삼성전자주식회사

Inventor： 강대혁 ,  홍창기 ,  이근택 ,  박임수 ,  한동균 ,  이몽섭 ,  오정민

IPC: H01L21/8242 ,  H01L27/108

CPC classification number: H01L28/91 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10852

Abstract: A method for manufacturing a semiconductor device is provided to obtain structural stability of a lower electrode by enlarging a lower part of an opening. An etch stop layer including a nitride and a mold layer including an oxide are formed on a substrate(100). An opening for exposing the substrate is formed by patterning the mold layer and the etch stop layer. A lateral part of the etch stop layer exposed through the opening is etched by using an etchant including H2SO4 and H2O so that a lower part of the opening defined by the etch stop layer is enlarged in comparison with a center part of the opening defined by the etch stop layer. A lower electrode(174) is formed on a surface of the opening having the enlarged lower part.

Abstract translation: 提供一种制造半导体器件的方法，通过扩大开口的下部来获得下电极的结构稳定性。 在衬底（100）上形成包括氮化物和包含氧化物的模具层的蚀刻停止层。 通过图案化模具层和蚀刻停止层来形成用于曝光衬底的开口。 通过使用包括H 2 SO 4和H 2 O的蚀刻剂蚀刻通过开口暴露的蚀刻停止层的侧面部分，使得由蚀刻停止层限定的开口的下部与由开口限定的开口的中心部分相比扩大 蚀刻停止层。 在具有扩大的下部的开口的表面上形成下电极（174）。

公开(公告)号：KR1020080010537A

公开(公告)日：2008-01-31

申请号：KR1020060070629

申请日：2006-07-27

Applicant: 삼성전자주식회사

Inventor： 임종흔 ,  홍창기 ,  윤보언 ,  윤성규 ,  한상엽

IPC: H01L21/027 ,  H01L21/32

CPC classification number: G03F7/0002 ,  H01L21/32135

Abstract: A method for forming a fine pattern is provided to form a fine pattern without distortion by performing an imprint method and an electrochemical mechanical polishing process. A method for forming a fine pattern comprises the steps of: preparing a substrate having a conductive film; forming an electro-shielding pattern on the conductive film, wherein the electro-shielding pattern partially exposes the conductive film; and forming a conductive pattern by performing an electrochemical mechanical polishing process for the exposed parts of the conductive film to be removed. The electro-shielding pattern includes Alkanethiol and is coated with Alkanethiol in a monolayer or a multilayer.

Abstract translation: 提供形成精细图案的方法以通过执行压印方法和电化学机械抛光工艺形成没有变形的精细图案。 形成精细图案的方法包括以下步骤：制备具有导电膜的衬底; 在导电膜上形成电屏蔽图案，其中电屏蔽图案部分地暴露导电膜; 以及通过对待除去的导电膜的暴露部分进行电化学机械抛光工艺来形成导电图案。 电屏蔽图案包括烷硫醇并且在单层或多层中涂覆有烷硫醇。

公开(公告)号：KR1020080006861A

公开(公告)日：2008-01-17

申请号：KR1020060066143

申请日：2006-07-14

Applicant: 삼성전자주식회사

Inventor： 오정민 ,  한정남 ,  홍창기 ,  이근택 ,  김영옥

IPC: H01L21/304

Abstract: A method for drying a semiconductor substrate and an apparatus for performing the same are provided to prevent the leaning effect of a capacitor caused by surface tension of water in a Marangoni dryer. A dipping process is performed to dip a semiconductor substrate into a receptacle with alcohol of a liquid state(S100). A moisture removal process is performed to remove moisture from the semiconductor substrate by removing relatively the alcohol with respect to the substrate dipped into the alcohol of the receptacle(S110). An alcohol removal process is performed to remove the remaining alcohol by dipping the substrate into an organic solvent including fluorine(S120). The alcohol includes isopropyl alcohol.

Abstract translation: 提供干燥半导体基板的方法及其执行装置，以防止Marangoni干燥器中由水的表面张力引起的电容器的倾斜效应。 进行浸渍处理以将半导体衬底浸入具有液态醇的容器中（S100）。 通过相对于浸入容器的醇中的基材去除相对于醇的水分，从而从半导体衬底去除水分（S110）。 通过将基材浸渍到包含氟的有机溶剂中来进行醇去除过程以除去剩余的醇（S120）。 酒精包括异丙醇。

公开(公告)号：KR1020080003616A

公开(公告)日：2008-01-08

申请号：KR1020060062069

申请日：2006-07-03

Applicant: 삼성전자주식회사

Inventor： 윤성규 ,  한상엽 ,  홍창기 ,  윤보언 ,  이재동 ,  박진구 ,  홍의관

IPC: H01L21/304

Abstract: A silica slurry containing a hydro peroxide for CMP(Chemical Mechanical Polishing) of semiconductor devices is provided to reduce generation of organic defects and to improve productivity and yield of the semiconductor devices by making a silicon surface have hydrophilicity after completing the CMP. A silica slurry for CMP of semiconductor devices includes fumed silica particles. A wafer is introduced into a CMP equipment(S10). The wafer is polished by using the silica slurry containing a hydro peroxide(S20). The wafer is cleaned by using a cleaning solution containing hydrofluoric acid(S30). The wafer is cleaned by using deionized water(S40). The wafer is dried(S50). The wafer is withdrawn from the CMP equipment(S60). The fumed silica particles are 0.1 to 50 wt% of a total slurry. A silical particle is over 10 wt% of the total slurry. The hydro peroxide is 0.1 to 3 vol%.

Abstract translation: 提供含有用于半导体器件的CMP（化学机械抛光）的过氧化氢的二氧化硅浆料，以通过在完成CMP之后使硅表面具有亲水性来减少有机缺陷的产生并提高半导体器件的生产率和产率。 用于半导体器件的CMP的二氧化硅浆料包括热解二氧化硅颗粒。 将晶片引入到CMP设备中（S10）。 通过使用含有过氧化氢的二氧化硅浆料对晶片进行抛光（S20）。 使用含有氢氟酸的清洗液清洗晶片（S30）。 用去离子水清洗晶片（S40）。 将晶片干燥（S50）。 从CMP设备中取出晶片（S60）。 热解法二氧化硅颗粒为总泥浆的0.1-50重量％。 硅质颗粒占总浆料的10重量％以上。 过氧化氢为0.1〜3体积％。

公开(公告)号：KR1020070120362A

公开(公告)日：2007-12-24

申请号：KR1020060055029

申请日：2006-06-19

Applicant: 삼성전자주식회사

Inventor： 이종원 ,  홍창기 ,  윤보언

IPC: C09K3/14

CPC classification number: H01L21/7684 ,  C09G1/02 ,  C09K3/1409 ,  C09K3/1463 ,  H01L21/3212

Abstract: A slurry for polishing metal wiring is provided to form metal wiring stably by inhibiting excessive corrosion of the metal wiring while improving a polishing rate of the metal wiring during a semiconductor manufacture process. A slurry for polishing metal wiring includes an oxidant, a corrosion inhibitor, and a polishing rate improver. The polishing rate improver is a compound having at least one nitrogen atom within an aromatic ring, wherein the nitrogen atom is not directly bond to a hydrogen atom capable of being dissociated into proton within slurry and has at least one lone pair. The polishing rate improver is a pyrimidine, pyrazole, pyridazine, pyrazine, pyridine, triazine, triazole, thiazole, thiadiazole, or imidazole-based compound.

Abstract translation: 提供用于研磨金属布线的浆料，通过在半导体制造过程中改善金属布线的抛光速率，同时抑制金属布线的过度腐蚀，从而稳定地形成金属布线。 用于抛光金属布线的浆料包括氧化剂，防腐蚀剂和抛光速率改进剂。 抛光速率改进剂是在芳香环中具有至少一个氮原子的化合物，其中氮原子不直接键合到能够在浆料内解离成质子的氢原子，并且具有至少一个孤对。 抛光速率改进剂是嘧啶，吡唑，哒嗪，吡嗪，吡啶，三嗪，三唑，噻唑，噻二唑或咪唑类化合物。

公开(公告)号：KR100785458B1

公开(公告)日：2007-12-13

申请号：KR1020050041568

申请日：2005-05-18

Applicant: 삼성전자주식회사

Inventor： 최석헌 ,  배병재 ,  손윤호 ,  홍창기 ,  박정헌

IPC: H01L27/105 ,  H01L21/304

CPC classification number: H01L27/11507 ,  G11C11/22 ,  H01L27/11502 ,  H01L28/55 ,  H01L28/75

Abstract: 향상된 특성을 갖는 강유전체 박막의 제조 방법 및 이를 이용한 반도체 장치의 제조 방법이 개시된다. 기판 상에 유기 금속 화학 기상 증착 공정으로 PZT를 증착하여 예비 강유전체막을 형성한 후, 기판이 장착되는 캐리어 및 예비 강유전체막의 표면에 접촉되는 연마 패드를 갖는 화학 기계적 연마 장치를 사용하고, 기판을 연마 패드에 접촉시키는 압력 및 연마 패드의 회전 속도를 조절하면서 예비 강유전체막의 표면을 연마하여 기판 상에 강유전체 박막을 형성한다. 연마된 강유전체 박막을 세정한 다음, 세정된 강유전체 박막을 큐어링한다. 적절한 공정 조건 하에서 표면 연마 공정을 적용하여 얇은 두께를 갖는 강유전체 박막을 구현할 수 있을 뿐만 아니라 강유전체 박막의 열화를 개선할 수 있다. 강유전체 박막의 데이터 보존력 또는 분극 보존력을 일정하게 유지시킬 수 있으며, 누설 전류 특성을 크게 향상시킬 수 있다.

公开(公告)号：KR1020070109694A

公开(公告)日：2007-11-15

申请号：KR1020060043035

申请日：2006-05-12

Applicant: 삼성전자주식회사

Inventor： 오정민 ,  한정남 ,  홍창기 ,  이근택 ,  강대혁 ,  심우관 ,  이종원

IPC: H01L27/115

CPC classification number: H01L27/115 ,  H01L21/76229 ,  H01L27/11568 ,  H01L21/28282

Abstract: A method for manufacturing a SONOS(Silicon Oxide Nitride Oxide Semiconductor) type non-volatile memory device is provided to prevent plasma-etching damage and to improve charge trap characteristics by using a silicon nitride layer having a charge trap layer pattern. A trench is formed on a substrate(100). The trench is buried sufficiently and an isolation layer(108) is formed on the substrate. A first thin film including an insulating material is formed on the substrate which is exposed by the isolation layer. A second thin film pattern including silicon nitride is formed on the first thin film. A third thin film as a dielectric layer is formed on the resultant structure including the second thin film pattern and the isolation layer. A fourth thin film including a conductive material is formed on the third thin film. A gate structure(150) including a tunnel insulating layer pattern of the first thin film, a charge trap layer pattern of the second thin film pattern, a blocking insulating layer pattern of the third thin film, and a gate electrode of the fourth thin film is formed by patterning the four thin film, the third thin film, the second thin film pattern, and the first thin film. A source/drain(130) is formed under the surface of the substrate adjacent to the gate structure.

Abstract translation: 提供一种用于制造SONOS（氧化硅氮化物半导体）型非易失性存储器件的方法，以通过使用具有电荷陷阱层图案的氮化硅层来防止等离子体蚀刻损伤并改善电荷陷阱特性。 在衬底（100）上形成沟槽。 沟槽被充分地埋入，并且在衬底上形成隔离层（108）。 在由隔离层露出的基板上形成包括绝缘材料的第一薄膜。 在第一薄膜上形成包括氮化硅的第二薄膜图案。 在包括第二薄膜图案和隔离层的所得结构上形成作为电介质层的第三薄膜。 在第三薄膜上形成包括导电材料的第四薄膜。 包括第一薄膜的隧道绝缘层图案，第二薄膜图案的电荷陷阱层图案，第三薄膜的阻挡绝缘层图案和第四薄膜的栅电极的栅极结构（150） 通过对四个薄膜，第三薄膜，第二薄膜图案和第一薄膜进行图案化而形成。 源极/漏极（130）形成在与栅极结构相邻的衬底的表面下方。

公开(公告)号：KR100752642B1

公开(公告)日：2007-08-29

申请号：KR1020050009683

申请日：2005-02-02

Applicant: 삼성전자주식회사

Inventor： 심우관 ,  오정민 ,  홍창기 ,  최상준 ,  김상용

IPC: H01L27/04 ,  H01L27/108

CPC classification number: H01L28/91 ,  H01L27/10852

Abstract: 하부전극의 기울어짐(leaning)이나 전기적인 쇼트(short)를 방지할 수 있는 커패시터의 제조방법에 대해 개시한다. 그 방법은 몰드산화막의 상부에 하부의 콘택플러그를 중심으로 연결되는 메쉬 형태의 브릿지용 절연막을 형성한 다음, 몰드산화막과 브릿지용 절연막을 식각하여 전극영역을 한정한 후, 몰드산화막과 브릿지용 절연막의 식각선택비가 500 이상인 식각기체를 이용하여 몰드산화막을 제거하는 것을 포함한다.
하부전극, 브릿지용 절연막, 몰드산화막, 식각선택비

公开(公告)号：KR100734464B1

公开(公告)日：2007-07-03

申请号：KR1020060064970

申请日：2006-07-11

Applicant: 삼성전자주식회사

Inventor： 차지훈 ,  홍창기 ,  이근택 ,  심우관 ,  문창섭 ,  최호욱

IPC: H01L21/027

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/3088 ,  H01L21/32139 ,  H01L21/31144

Abstract: A method for forming a hard mask of a fine pitch and a method for forming a micro pattern of a semiconductor device using the same are provided to overcome easily the limitation of resolution in a photolithography process by using two-step mask pattern forming processes capable of forming first mask patterns and second mask patterns between the first mask patterns. A hard mask layer(20) is formed on a substrate. A plurality of first mask patterns(30) are formed on the hard mask layer. A buffer layer(40) for defining a recess between adjacent first mask patterns is formed along an upper surface of the resultant structure. A second mask pattern(50a) is formed in the recess of the buffer layer. The buffer layer is partially removed from the resultant structure, so that upper surfaces of the first mask patterns are exposed to the outside. The hard mask layer is exposed to the outside between the first and second mask patterns by removing the buffer layer using the first and second mask patterns as an etch mask. A hard mask pattern is formed on the resultant structure by etching the exposed portion of the hard mask layer using the first and second mask patterns as an etch mask.

Abstract translation: 提供一种用于形成精细间距的硬掩模的方法以及使用其形成半导体器件的微图形的方法，以便通过使用两步掩模图案形成方法容易地克服光刻工艺中的分辨率的限制， 在第一掩模图案之间形成第一掩模图案和第二掩模图案。 在基板上形成硬掩模层（20）。 在硬掩模层上形成多个第一掩模图案（30）。 沿所得结构的上表面形成用于限定相邻的第一掩模图案之间的凹部的缓冲层（40）。 第二掩模图案（50a）形成在缓冲层的凹部中。 缓冲层从所得到的结构部分去除，使得第一掩模图案的上表面暴露于外部。 通过使用第一和第二掩模图案作为蚀刻掩模去除缓冲层，将硬掩模层暴露于第一和第二掩模图案之间的外部。 通过使用第一和第二掩模图案作为蚀刻掩模蚀刻硬掩模层的暴露部分，在所得结构上形成硬掩模图案。