公开(公告)号：KR1020090081153A

公开(公告)日：2009-07-28

申请号：KR1020080007082

申请日：2008-01-23

Applicant: 삼성전자주식회사

Inventor： 이창범 ,  박영수 ,  선우문욱 ,  이명재 ,  강보수 ,  안승언 ,  김기환

IPC: H01L27/108

CPC classification number: H01L27/24 ,  G11C13/00 ,  G11C13/0007 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71 ,  G11C2213/72

Abstract: A resistivity memory device and a manufacturing method thereof by using the resistance of the resistance alteration material are provided to maintain the resistance law of the first resistance alteration layer although the lateral part of the first resistance alteration layer is damaged by etching. A resistivity memory device comprises a first electrode(100), a first insulation layer, a first resistance alteration layer(120) and a first switching device. The first insulation layer is equipped on the first electrode. The first insulation layer has the first hole exposing a part of the first electrode. The first resistance alteration layer is contacted with the exposed first electrode. The first resistance alteration layer is expanded on the first insulation layer of the first around hole. The first switching device is electrically connected to the first resistance alteration layer.

Abstract translation: 提供了使用电阻变化材料的电阻的电阻率存储装置及其制造方法，以保持第一电阻改变层的电阻定律，尽管第一电阻改变层的侧面部分被蚀刻损坏。 电阻率存储器件包括第一电极（100），第一绝缘层，第一电阻改变层（120）和第一开关器件。 第一绝缘层装配在第一电极上。 第一绝缘层具有暴露第一电极的一部分的第一孔。 第一电阻改变层与暴露的第一电极接触。 第一电阻改变层在第一周围孔的第一绝缘层上扩展。 第一开关装置电连接到第一电阻改变层。

公开(公告)号：KR1020090045653A

公开(公告)日：2009-05-08

申请号：KR1020070111584

申请日：2007-11-02

Applicant: 삼성전자주식회사

Inventor： 김기환 ,  박영수 ,  강보수 ,  이명재 ,  이창범

IPC: H01L27/115 ,  H01L21/8247

CPC classification number: G11C11/36 ,  G11C11/14 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/003 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/32 ,  G11C2213/71 ,  G11C2213/72 ,  G11C2213/73 ,  G11C2213/76 ,  H01L27/1021 ,  H01L21/28273

Abstract: 본 발명은 고밀도 비휘발성 메모리 소자를 구현하기 위하여 별도로 형성된 스위칭 소자가 필요없이 간단한 구조로 구동할 수 있는 다이오드 특성을 지닌 비휘발성 메모리 소자 및 이를 포함하는 메모리 어레이에 관한 것이다. 제 1전극; 상기 제1전극 상에 형성된 다이오드-스토리지 노드; 및 상기 다이오드-스토리지 노드 상에 형성된 제 2전극;을 포함하는 비휘발성 메모리 소자를 제공한다.
저항 변화 메모리, 다이오드, 비휘발성 메모리, 크로스 포인트

公开(公告)号：KR1020090022186A

公开(公告)日：2009-03-04

申请号：KR1020070087307

申请日：2007-08-29

Applicant: 삼성전자주식회사

Inventor： 김선일 ,  이재철 ,  송이헌 ,  박영수 ,  김창정 ,  박재철

IPC: H01L29/786

CPC classification number: H01L29/7869 ,  H01L21/02554 ,  H01L21/02565 ,  H01L21/02581 ,  H01L29/78696

Abstract: An oxide thin film transistor and a manufacturing method thereof are provided to improve electrical characteristic by forming a capping layer with high work function in a channel region. A channel(14) and a capping layer(15) with a work function higher than the channel are consecutively formed in the position corresponding to a gate(12). A gate insulator(13) is formed between the gate and the channel. A source(16a) and a drain(16b) are formed while contacting two parts of the capping layer. A passivation layer is formed by coating the insulating material on the capping layer. The channel is made of the In-Zn oxide coated with Ni.

Abstract translation: 提供一种氧化物薄膜晶体管及其制造方法，通过在沟道区域形成具有高功函数的覆盖层来提高电气特性。 具有比通道高的功函数的通道（14）和盖层（15）在对应于门（12）的位置处连续地形成。 栅极绝缘体（13）形成在栅极和沟道之间。 形成源极（16a）和漏极（16b），同时接触覆盖层的两个部分。 通过在绝缘层上涂覆绝缘材料形成钝化层。 该通道由镀Ni的In-Zn氧化物制成。

公开(公告)号：KR1020080112877A

公开(公告)日：2008-12-26

申请号：KR1020070061875

申请日：2007-06-22

Applicant: 삼성전자주식회사

Inventor： 김창정 ,  박영수 ,  이은하 ,  박재철

IPC: H01L29/786 ,  H01L21/302

CPC classification number: C09K13/06 ,  H01L21/467 ,  H01L29/7869

Abstract: An etching solution of a Zn oxide and a Zn oxide thin film transistor are provided to remove damage area formed in a channel in a source and drain forming process as a channel surface is partly removed and a recessed portion is formed. A Zn oxide thin film transistor comprises a gate(32), a channel(34), a gate insulator, a source(35a), a drain(35b), and a recessed portion(R). The channel is formed of a Zn oxide in a location corresponding to the gate. The gate insulator is formed between the gate and channel. The source and drain are formed with contacting two part of the channel. The recessed portion is formed in the channel between the drain and source.

Abstract translation: 提供Zn氧化物和Zn氧化物薄膜晶体管的蚀刻溶液以去除在源极和漏极形成过程中形成的沟道中的损伤区域，因为部分地去除沟道表面并形成凹陷部分。 Zn氧化物薄膜晶体管包括栅极（32），沟道（34），栅极绝缘体，源极（35a），漏极（35b）和凹陷部分（R）。 沟道由与栅极对应的位置的Zn氧化物形成。 栅极绝缘体形成在栅极和沟道之间。 源极和漏极形成为接触通道的两部分。 凹陷部分形成在漏极和源极之间的沟道中。

公开(公告)号：KR1020080112609A

公开(公告)日：2008-12-26

申请号：KR1020070061207

申请日：2007-06-21

Applicant: 삼성전자주식회사

Inventor： 이명재 ,  김동욱 ,  박영수 ,  서순애 ,  박배호 ,  강보수 ,  안승언 ,  이창범

IPC: H01L27/115 ,  B82Y40/00

CPC classification number: G11C13/0004 ,  B82Y10/00

Abstract: A resistivity memory device and manufacturing method thereof are provided to control the location and form of an overhanging construction selectively and arbitrarily by providing various manufacturing methods of the overhanging construction formed in a middle electrode. A resistivity memory device comprises a middle electrode(32), a resistance conversion layer(33) and an upper electrode(34). The middle electrode is formed on a switch(31). The middle electrode is composed of a overhanging construction(p). The resistance conversion layer is formed on the middle electrode. The upper electrode is formed on the resistance conversion layer.

Abstract translation: 提供一种电阻率记忆装置及其制造方法，通过提供形成在中间电极中的突出结构的各种制造方法，有选择地和任意地控制悬垂结构的位置和形状。 电阻率存储器件包括中间电极（32），电阻转换层（33）和上电极（34）。 中间电极形成在开关（31）上。 中间电极由突出构造（p）组成。 电阻转换层形成在中间电极上。 上电极形成在电阻转换层上。

公开(公告)号：KR1020080075405A

公开(公告)日：2008-08-18

申请号：KR1020070014553

申请日：2007-02-12

Applicant: 삼성전자주식회사

Inventor： 후아샹잉 ,  박영수 ,  선우문욱

IPC: H01L27/115

CPC classification number: H01L27/0688 ,  H01L21/8221 ,  H01L27/11521 ,  H01L27/11551 ,  H01L29/7854 ,  H01L21/28273

Abstract: A non-volatile memory transistor having a polysilicon fin, a stacked non-volatile memory device having the transistors, a method of manufacturing the transistor, and a method of manufacturing the memory device are provided to reduce a leakage current and increase an on-current and a program/erasure window by forming a pillar type polysilicon fin in the non-volatile memory transistor. A non-volatile memory device includes an active fin(100a), a first charge storage pattern(117'), a first control gate line(119c), an interlayer dielectric(120), a polysilicon fin(135a), a second charge storage pattern(137'), and a second control gate line(139c). The active fin is protruded upwards from a semiconductor substrate. The first charge storage pattern covers an upper surface and a sidewall of the active fin. The first control gate line covers the upper surface of the first charge storage pattern and traverses an upper surface of the active fin. The interlayer dielectric is arranged on the first control gate line. The polysilicon fin is arranged on the interlayer dielectric. The second charge storage pattern covers the upper surface and the sidewall of the polysilicon fin. The second control gate line covers the upper surface of the second charge storage pattern and traverses the upper portion of the polysilicon fin.

Abstract translation: 提供具有多晶硅鳍片的非易失性存储晶体管，具有晶体管的堆叠非易失性存储器件，晶体管的制造方法和制造存储器件的方法，以减少漏电流并增加导通电流 以及通过在非易失性存储晶体管中形成柱状多晶硅鳍的程序/擦除窗口。 非易失性存储器件包括有源鳍片（100a），第一电荷存储图案（117），第一控制栅极线（119c），层间电介质（120），多晶硅鳍片（135a），第二电荷 存储图案（137'）和第二控制栅极线（139c）。 活性鳍片从半导体衬底向上突出。 第一电荷存储图案覆盖有源鳍片的上表面和侧壁。 第一控制栅极线覆盖第一电荷存储图案的上表面并且穿过有源鳍片的上表面。 层间电介质布置在第一控制栅极线上。 多晶硅鳍布置在层间电介质上。 第二电荷存储图案覆盖多晶硅鳍片的上表面和侧壁。 第二控制栅极线覆盖第二电荷存储图案的上表面并穿过多晶硅鳍片的上部。

公开(公告)号：KR100841641B1

公开(公告)日：2008-06-26

申请号：KR1020050127530

申请日：2005-12-22

Applicant: 삼성전자주식회사

Inventor： 김영호 ,  박영수 ,  정준영 ,  김주필 ,  이근호 ,  최준영 ,  이재과 ,  주판유 ,  강현정

IPC: H04W4/02

CPC classification number: G06Q30/02

Abstract: 본 발명은 광대역 무선접속 통신시스템을 이용한 위치정보기반 광고정보제공을 위한 장치 및 방법에 관한 것으로 광대역 무선접속 통신시스템을 이용한 위치정보기반 광고대상정보를 제공하는 광고정보제공 시스템에 있어서, 사업자 서버로 광고대상정보를 제공하는 매장 단말기와, 상기 매장 단말기가 제공한 상기 광고대상정보를 과금대상정보로 사용하고, 사용자 단말기로 길안내 정보를 제공하는 사업자 서버와, 상기 사업자 서버로부터 광고대상정보를 제공받아, 사용자 단말기로 상기 광고대상정보를 방송 또는 선택전송하고, 상기 사용자단말기로부터의 길안내 승인정보를 상기 사업자서버로 전송하는 기지국과, 상기 기지국으로부터 광고대상정보를 수신하고, 상기 사업자서버로부터 길안내정보를 수신하여 길안내기능을 구동하는 사용자 단말기를 포함하는 것으로 사용자의 선택에 따른 광고정보 또는 방송광고정보와 길안내 정보를 제공하여 사용자에게 편리한 서비스를 제공할 수 있는 이점이 있다. 또한, 광대역 무선접속 통신망을 이용하여 광고대상정보를 전송하므로 이동통신망을 이용한 서비스보다 양질의 광고정보를 전송할 수 있는 이점이 있다.
광대역 무선접속 통신시스템, 사용자 단말기, IEEE 802.16, 사업자서버, 기지국. 제어국.

公开(公告)号：KR1020080044479A

公开(公告)日：2008-05-21

申请号：KR1020060113385

申请日：2006-11-16

Applicant: 삼성전자주식회사

Inventor： 이명재 ,  박영수 ,  정란주 ,  서순애 ,  김동철 ,  안승언

IPC: H01L27/105

CPC classification number: H01L45/04 ,  H01L27/2436 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1625

Abstract: A resistive memory device having transition metal solid solution and a method for manufacturing the same are provided to obtain stable set voltage, reset voltage, and resistance characteristics during an operation. A resistive memory device having transition metal solid solution includes a lower electrode(21), a solid solution layer(24), a resistive layer(22), and a upper electrode(23). The solid solution layer is formed on the lower electrode. The resistive layer is formed on the solid solution layer. The upper electrode is formed on the resistive layer. The solid solution layer is a transition metal solid solution. The resistive layer is formed of a transition metal oxide. The transition metal oxide includes at least one of Ni oxide, Ti oxide, Hf oxide, Zr oxide, Zn oxide, W oxide, Co oxide, or Nb oxide.

Abstract translation: 提供具有过渡金属固溶体的电阻式存储器件及其制造方法，以在操作期间获得稳定的设定电压，复位电压和电阻特性。 具有过渡金属固溶体的电阻式存储器件包括下电极（21），固溶层（24），电阻层（22）和上电极（23）。 固溶层形成在下电极上。 电阻层形成在固溶层上。 上电极形成在电阻层上。 固溶层为过渡金属固溶体。 电阻层由过渡金属氧化物形成。 过渡金属氧化物包括Ni氧化物，Ti氧化物，Hf氧化物，Zr氧化物，Zn氧化物，W氧化物，Co氧化物或Nb氧化物中的至少一种。

公开(公告)号：KR1020080021392A

公开(公告)日：2008-03-07

申请号：KR1020060084758

申请日：2006-09-04

Applicant: 삼성전자주식회사

Inventor： 이윤희 ,  최삼종 ,  조규철 ,  강태수 ,  박영수 ,  김연숙

IPC: H01L23/544

CPC classification number: H01L23/544 ,  H01L21/67282 ,  H01L2223/54413 ,  H01L2223/54493

Abstract: A semiconductor wafer with an identification part is provided to prevent residues from remaining on an identification part by including an identification part located in a position from the outer circumference of a semiconductor wafer to a position not deeper than the depth of a notch wherein the identification part is adjacent to the notch. A notch(110) is formed of an empty space positioned at one part of the edge of a body(102) of a flat plate, having a predetermined depth(D) facing toward the center of the body. An identification part(120) is formed in the surface of the body adjacent to the notch, located in a distance from the outer circumference of the body to a position not deeper than the depth of the notch. The notch can be an open space of a V shape, having first and second sides(112,114) confronting each other.

Abstract translation: 提供了具有识别部件的半导体晶片，通过将位于半导体晶片的外周的位置的识别部位设置在不比凹口的深度更深的位置上，将识别部件残留在识别部上， 与凹口相邻。 凹口（110）由位于平板的本体（102）的边缘的一部分处的空的空间形成，具有面向主体中心的预定深度（D）。 识别部分（120）形成在与凹口相邻的主体的表面中，所述凹口位于距离主体的外周一定距离至不比切口的深度更深的位置。 凹口可以是具有彼此面对的第一和第二侧面（112,114）的V形开放空间。

公开(公告)号：KR1020070076850A

公开(公告)日：2007-07-25

申请号：KR1020060006246

申请日：2006-01-20

Applicant: 삼성전자주식회사

Inventor： 이윤희 ,  박영수 ,  조규철 ,  강태수 ,  최수열 ,  전태훈 ,  차혜진

IPC: H01L21/20

CPC classification number: H01L21/7624 ,  H01L21/02381 ,  H01L21/324 ,  H01L21/76877

Abstract: A SOI(Silicon On Insulator) substrate and a manufacturing method thereof are provided to radiate the heat generated from a device onto a lower silicon substrate through silicon plugs. An insulating layer(220) is formed on a first silicon substrate(210), and then is etched to form plural contact holes exposing the first silicon substrate. The exposed silicon substrate is selectively epitaxially grown to plural silicon plugs(225) which fill the contact holes. The first silicon substrate is connected to a second silicon substrate via the silicon plugs formed on the insulating layer. The insulating layer is formed by subjecting a thermal oxidation process on the first silicon substrate.

Abstract translation: 提供SOI（绝缘体上硅）衬底及其制造方法，以通过硅插头将从器件产生的热辐射到下硅衬底上。 绝缘层（220）形成在第一硅衬底（210）上，然后被蚀刻以形成暴露第一硅衬底的多个接触孔。 暴露的硅衬底被选择性地外延生长到填充接触孔的多个硅插头（225）。 第一硅衬底经由形成在绝缘层上的硅插头连接到第二硅衬底。 通过在第一硅衬底上进行热氧化处理来形成绝缘层。