PROCEDE DE FORMATION D'UN CAPTEUR D'IMAGES ECLAIRE PAR LA FACE ARRIERE

    公开(公告)号:FR2954587A1

    公开(公告)日:2011-06-24

    申请号:FR0957950

    申请日:2009-11-10

    Abstract: L'invention concerne un procédé de fabrication d'un capteur d'images éclairé par la face arrière, comprenant les étapes suivantes : (a) former, dans et sur une couche de silicium (14) de type SOI, des composants de capture et de transfert de porteurs photo-générés (24, 26, 27) et des régions d'isolement (28) ; (b) former un empilement de niveaux d'interconnexion (16) sur la couche de silicium (14) et fixer, sur l'empilement d'interconnexion, une poignée semiconductrice (22) ; (c) éliminer le support semiconducteur (10) ; (d) former, dans la couche isolante (12) et la couche de silicium (14), des tranchées (42, 44) atteignant les régions d'isolement ; (e) déposer une couche de silicium amorphe fortement dopée (46) sur les parois et le fond des tranchées et faire cristalliser ladite couche de silicium amorphe (48) ; et (f) remplir les tranchées d'un matériau réfléchissant (50).

    84.
    发明专利
    未知

    公开(公告)号:FR2905519B1

    公开(公告)日:2008-12-19

    申请号:FR0653524

    申请日:2006-08-31

    Abstract: A method for manufacturing an integrated circuit containing fully and partially depleted MOS transistors, including the steps of forming similar MOS transistors on a thin silicon layer formed on a silicon-germanium layer resting on a silicon substrate; attaching the upper surface of the structure to a support wafer; eliminating the substrate; depositing a mask and opening this mask at the locations of the fully-depleted transistors; oxidizing the silicon-germanium at the locations of the fully-depleted transistors in conditions such that a condensation phenomenon occurs; and eliminating the oxidized portion and the silicon-germanium portion, whereby there remain transistors with a thinned silicon layer.

    87.
    发明专利
    未知

    公开(公告)号:FR2858877B1

    公开(公告)日:2005-10-21

    申请号:FR0350418

    申请日:2003-08-11

    Abstract: A method for forming a heterojunction bipolar transistor including the steps of: forming in a semiconductor substrate a collector area of a first doping type; growing by epitaxy above a portion of the collector area a silicon/germanium layer of a second doping type forming a base area; forming above the silicon/germanium layer a sacrificial emitter formed of a material selectively etchable with respect to the silicon/germanium layer and with respect to the layers and consecutively-formed insulating spacers; forming first insulating spacers on the sides of the sacrificial emitter; growing by epitaxy a silicon layer above the exposed portions of the silicon/germanium layer; forming second insulating spacers adjacent to the first spacers and laid on the silicon layer; covering the entire structure with an insulating layer; partially removing the insulating layer above the sacrificial emitter and removing the sacrificial emitter; filling the space previously taken up by the sacrificial emitter with a semiconductor material of the first doping type.

    88.
    发明专利
    未知

    公开(公告)号:FR2867610A1

    公开(公告)日:2005-09-16

    申请号:FR0450483

    申请日:2004-03-10

    Abstract: The integral condenser, formed in the upper part of a semiconductor substrate (20) comprising at least one lightly-doped type N semiconductor layer (24) with its upper surface having a highly-doped type P region (35) bounded by an insulation zone (34), has one contact in the form of a metal layer (44) buried immediately beneath the type N semiconductor layer, and at least one vertical metal contact passing through the semiconductor layer as far as the metal layer and reaching the surface of the semiconductor layer outside the type P region. The metal layer and contact are of the same metal, selected from the group comprising tungsten, titanium nitrate, titanium, copper and their alloys. An independent claim is also included for the condenser fabrication process.

    90.
    发明专利
    未知

    公开(公告)号:FR2779572B1

    公开(公告)日:2003-10-17

    申请号:FR9807059

    申请日:1998-06-05

    Abstract: A vertical bipolar transistor production process comprises epitaxy of a single crystal silicon emitter region in direct contact with the upper layer of a silicon germanium heterojunction base. Production of a vertical bipolar transistor comprises (a) forming an intrinsic collector (4) on an extrinsic collector layer buried in a semiconductor substrate (1); (b) forming a lateral insulation region (5) around the upper part of the intrinsic collector and an offset extrinsic collector well (60); (c) forming an silicon germanium heterojunction base above the intrinsic collector (4) and the lateral insulation region (5) by non-selective epitaxy of a multilayer (8) including a silicon germanium layer; and (e) forming an in-situ doped emitter by epitaxy on a window of the surface of the multilayer located above the intrinsic collector to obtain, above the window, a single crystal silicon emitter region in direct contact with the upper layer of the multilayer (8). An Independent claim is also included for a vertical bipolar transistor produced by the above process.

Patent Agency Ranking